NAND flash memory programming

1. A method of performing a write operation on a memory cell, comprising: applying a programming voltage to a control gate of the memory cell; and ungrounding a channel of the memory cell during the write operation such that loss of electrons from the channel as they tunnel into a charge storage structure of the memory cell will result in a more positively charged channel.

2. The method of claim 1 , wherein the channel is formed in a semiconductor material.

3. The method of claim 2 , wherein the channel is formed in a substrate.

4. The method of claim 1 , wherein the charge storage structure comprises a floating gate.

5. The method of claim 1 , and further comprising causing the channel of the memory cell to have a channel voltage.

6. The method of claim 5 , and further comprising floating the channel voltage while the control gate is at the programming voltage.

7. The method of claim 6 , and further comprising floating a voltage on at least one of a source line or a drain line electrically coupled to the channel of the memory cell.

8. A method comprising: applying a programming voltage to a control gate of a memory cell in a string of memory cells; turning on a select transistor coupled to the string; and turning off the select transistor as the control gate reaches a voltage sufficient to cause electron tunneling from a channel of the memory cell onto a charge storage structure of the memory cell.

9. The method of claim 8 , wherein the select transistor comprises a drain select gate (SGD) transistor.

10. A method comprising: applying a programming voltage to a control gate of a memory cell that is part of a series of memory cells including a select gate drain transistor; ungrounding a channel of the memory cell and allowing the channel to remain ungrounded during a portion of a programming operation; and turning off the select gate drain transistor as the control gate of the memory cell reaches a sufficient voltage to cause electron tunneling from the channel of the memory cell to a floating gate of the memory cell.

11. The method of claim 10 , wherein allowing the channel of the cell to remain ungrounded during the portion of the programming operation comprises allowing the channel of the cell to remain ungrounded before the programming voltage is applied.

12. The method of claim 10 , wherein allowing the channel of the cell to remain ungrounded during the portion of the programming operation comprises allowing the channel of the cell to remain ungrounded as the programming voltage is applied.

13. The method of claim 10 , wherein allowing the channel of the cell to remain ungrounded during the portion of the programming operation comprises providing a more positively charged channel than a floating gate of the memory cell.

14. The method of claim 10 , wherein a quantity of cycles of applying the programming voltage to the control gate of the memory cell is determined in response to whether the channel is ungrounded.

15. The method of claim 10 , wherein a quantity of cycles of applying the programming voltage to the control gate of the memory cell is determined in response to whether the source is ungrounded.

16. The method of claim 10 , wherein a quantity of cycles of applying the programming voltage to the control gate of the memory cell is determined in response to whether the drain is ungrounded.

17. The method of claim 10 , wherein allowing the channel of the memory cell to remain ungrounded during the portion of the programming operation comprises floating a voltage of a substrate comprising the channel.

18. The method of claim 17 , and further comprising: floating at least one of a bit line or source; and disconnecting at least one voltage from at least one of the source or a drain while the control gate is at the programming voltage.