A semiconductor memory apparatus includes a boundary circuit unit positioned between a low voltage page buffer and a high voltage page buffer and having circuits configured to electrically couple the low voltage page buffer and the high voltage page buffer. The boundary circuit unit includes: a first boundary circuit unit having first and second transistors configured to receive data of a corresponding memory cell area through a signal transmission line selected from a plurality of signal transmission lines extended and arranged along a first direction for each column; a second boundary circuit unit disposed adjacent in the first direction from the first boundary circuit unit and having the plurality of signal transmission lines extended and arranged thereon; and an active region where the first transistor is formed and an active region where the second transistor is formed are isolated from each other.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor memory apparatus comprising a boundary circuit unit positioned between a low voltage page buffer and a high voltage page buffer and having circuits configured to electrically couple the low voltage page buffer and the high voltage page buffer, wherein the boundary circuit unit comprises: a first boundary circuit unit comprising first and second transistors configured to receive data of a corresponding memory cell area through a signal transmission line selected from a plurality of signal transmission lines extended and arranged along a first direction for each column; and a second boundary circuit unit disposed adjacent in the first direction from the first boundary circuit unit and having the plurality of signal transmission lines extended and arranged thereon, and an active region where the first transistor is formed and an active region where the second transistor is formed are isolated from each other.
2. The semiconductor memory apparatus according to claim 1 , wherein the first boundary circuit unit comprises: first and second active regions arranged at a predetermined distance from each other along the first direction; a first transistor arranged over the first active region and having a first gate, disposed in a second direction crossing the first direction, and a first source and a first drain arranged in the first active region in both sides of the first gate; a second transistor arranged over the second active region and having a second gate, extended in the second direction, and a second source and a second drain arranged in the second active region in both sides of the second gate.
3. The semiconductor memory apparatus according to claim 2 , further comprising: an odd bit line electrically coupled to the first drain; and an even bit line electrically coupled to the second drain, wherein the odd bit line and the even bit line are arranged over the first and second boundary circuit units in parallel to the signal transmission line.
4. The semiconductor memory apparatus according to claim 3 , wherein the odd bit line and the even bit line are arranged on the same line, and electrically insulated from each other.
5. The semiconductor memory apparatus according to claim 3 , wherein the odd bit line and the even bit line are positioned in a column where the selected signal transmission line is to be formed, and a first portion of the selected signal transmission line is positioned in the prearranged column, and a second portion of the selected signal transmission line is bent to be positioned in an adjacent column.
6. The semiconductor memory apparatus according to claim 5 , wherein a signal transmission line positioned in the adjacent column comprises a cut portion to be isolated from the selected signal transmission line, and a portion of the signal transmission line positioned in the adjacent column electrically is coupled to another portion of the signal transmission line positioned in the adjacent column through an upper conductive interconnection formed over the signal transmission line.
7. The semiconductor memory apparatus according to claim 6 , wherein the second boundary circuit unit further comprises a plurality of upper interconnections positioned over the plurality of signal transmission lines.
8. The semiconductor memory apparatus according to claim 7 , wherein the plurality of upper interconnections and the upper conductive interconnection are positioned on the same level.
9. The semiconductor memory apparatus according to claim 7 , wherein each of the upper interconnections has a first portion and a second portion, the first portion and a corresponding signal transmission line overlap one another, the second portion is disposed in a space between the corresponding signal transmission line and another signal transmission line adjacent thereto; and a bent portion is formed between the first portion and the second portion.
10. A semiconductor memory apparatus comprising: a first boundary circuit unit comprising first and second transistors configured receive data of a corresponding memory cell area through a selected signal transmission line among a plurality of signal transmission lines extended in a first direction for each column; and a second boundary circuit unit having the plurality of signal transmission lines arranged thereon and extended to the first boundary circuit unit and comprising a plurality of upper interconnections overlapped over the plurality of signal transmission lines, wherein the selected signal transmission line comprises a first portion coupled to a source of the first transistor and a second portion coupled to a source of the second transistor, the first portion is positioned over a column corresponding to the selected signal transmission line, the second portion is positioned over a column where a signal transmission line adjacent to the selected signal transmission line is to be positioned such that the selected signal transmission line has a bent shape, and the signal transmission line positioned in the adjacent column comprises a cut portion to be isolated from the second portion of the selected signal transmission line.
11. The semiconductor memory apparatus according to claim 10 , wherein an active region where the first transistor is formed and an active region where the second transistor is formed are arranged at a predetermined distance from each other along the first direction.
12. The semiconductor memory apparatus according to claim 10 , further comprising: an odd bit line electrically coupled to a drain of the first transistor; and an even bit line electrically coupled to a drain of the second transistor, wherein the odd bit line and the even bit line are extended and arranged over the first and second boundary circuit units along the first direction.
13. The semiconductor memory apparatus according to claim 12 , wherein the odd bit line and the even bit line are arranged on the same line, and electrically insulated from each other.
14. The semiconductor memory apparatus according to claim 13 , wherein the first portion of the selected signal transmission line is disposed in a straight line shape.
15. The semiconductor memory apparatus according to claim 10 , wherein a portion of the signal transmission line positioned in the adjacent column electrically is coupled to another portion of the signal transmission line positioned in the adjacent column through an upper conductive interconnection formed over the signal transmission line.
16. The semiconductor memory apparatus according to claim 15 , wherein the plurality of upper interconnections and the upper conductive interconnection are positioned on the same level.
17. The semiconductor memory apparatus according to claim 10 , wherein each of the upper interconnections has a first portion and a second portion, the first portion and a corresponding signal transmission line overlap one another, the second portion is disposed in a space between the corresponding signal transmission line and another signal transmission line adjacent thereto, and a bent portion is formed between the first portion and the second portion.
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May 25, 2012
March 10, 2015
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