Disclosed herein is a semiconductor package including: a semiconductor chip having a bonding pad; and a first substrate including a rerouting layer having short type rerouting patterns electrically connected with the bonding pad and formed to be seamlessly connected with each other and a plurality of open type rerouting patterns separately formed on the same layer as the short type rerouting patterns and connection terminals for signal connection each formed on the open type rerouting patterns.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor package, comprising: a semiconductor chip having a bonding pad; and a first substrate including a rerouting layer having short type rerouting patterns electrically connected with the bonding pad and formed to be seamlessly connected with each other and a plurality of open type rerouting patterns separately formed on the same layer as the short type rerouting patterns and connection terminals for signal connection each formed on the open type rerouting patterns, wherein the plurality of open type rerouting patterns are formed for substantially transferring the same signal and are separated in a separate area, and another pattern formed on the same layer as the open type rerouting patterns crosses the separate area.
2. The semiconductor package as set forth in claim 1 , wherein the semiconductor package is a wafer level package (WLP).
3. The semiconductor package as set forth in claim 1 , wherein the semiconductor package is formed using a semiconductor wafer.
4. The semiconductor package as set forth in claim 1 , wherein the first substrate further includes: an insulating layer on which the rerouting layer is formed; and an external connection terminal formed in the short type rerouting pattern.
5. The semiconductor package as set forth in claim 4 , further comprising a solder resist layer having an opening part formed on the insulating layer to cover the rerouting layer and exposing a portion on which the external connection terminal and the connection terminals for signal connection are formed.
6. The semiconductor package as set forth in claim 4 , wherein the external connection terminal is a solder ball.
7. The semiconductor package as set forth in claim 1 , wherein the connection terminal for signal connection is a solder ball.
8. A semiconductor package module, comprising: a semiconductor package including a semiconductor chip having a bonding pad, and a first substrate including a rerouting layer having short type rerouting patterns electrically connected with the bonding pad and formed to be seamlessly connected with each other and a plurality of open type rerouting patterns separately formed on the same layer as the short type rerouting patterns and connection terminals for signal connection each formed on the open type rerouting patterns, the plurality of open type rerouting patterns being formed for substantially transferring the same signal and being separated in a separate area, and another pattern, formed on the same layer as the open type rerouting patterns, crossing the separate area; and a second substrate, on which the semiconductor package is mounted, having connection pads for signal connection to electrically connect the open type rerouting patterns separately formed by being bonded with the connection terminal for signal connection.
9. The semiconductor package module as set forth in claim 8 , wherein the semiconductor package is a wafer level package (WLP).
10. The semiconductor package module as set forth in claim 8 , wherein the semiconductor package is formed using a semiconductor wafer.
11. The semiconductor package module as set forth in claim 8 , wherein the first substrate further includes: an insulating layer on which the rerouting layer is formed; and an external connection terminal formed in the short type rerouting pattern.
12. The semiconductor package module as set forth in claim 11 , further comprising a solder resist layer having an opening part formed on the insulating layer to cover the rerouting layer and exposing a portion on which the external connection terminal and the connection terminals for signal connection are formed.
13. The semiconductor package module as set forth in claim 11 , wherein the external connection terminal is a solder ball.
14. The semiconductor package module as set forth in claim 8 , wherein the connection terminal for signal connection is a solder ball.
15. The semiconductor package module as set forth in claim 8 , wherein the second substrate is a printed circuit board (PCB).
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 8, 2012
March 24, 2015
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