A semiconductor memory device configured to apply a temperature-compensated word line voltage to a word line during a data read operation includes a memory cell array including a plurality of word lines, a plurality of non-volatile memory cells connected to the word lines, and a word line voltage application unit configured to apply a temperature-compensated read voltage to a selected word line and to apply a temperature-compensated pass voltage to at least one unselected word line during a read operation.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor memory device, comprising: a memory cell array including a plurality of word lines and a plurality of non-volatile memory cells connected to the word lines; and a word line voltage application unit configured to apply a temperature-compensated read voltage to a selected word line of the plurality of word lines, and to apply a temperature-compensated pass voltage to at least one unselected word line of the plurality of word lines during a read operation, wherein at least one of the plurality of non-volatile memory cells has a plurality of threshold voltage levels, and the word line voltage application unit is configured to apply temperature-compensated pass voltages corresponding to respective threshold voltage levels.
2. The device of claim 1 , wherein the word line voltage application unit comprises: a word line voltage generator configured to detect a temperature and output the temperature-compensated read voltage and the temperature-compensated pass voltage corresponding to the temperature; and a row decoder configured to apply the read voltage to the selected word line, and to apply the pass voltage to the at least one unselected word line.
3. The device of claim 2 , wherein the word line voltage generator comprises: a temperature detector configured to detect the temperature; a first lookup table configured to store first temperature compensation data for temperature-compensating the pass voltage according to the temperature; a second lookup table configured to store second temperature compensation data for temperature-compensating the read voltage according to the temperature; a compensator configured to read the first temperature compensation data and the second temperature compensation data corresponding to the temperature, and to output a pass voltage compensation signal corresponding to the first temperature compensation data and a read voltage compensation signal corresponding to the second temperature compensation data; a pass voltage generator configured to output the pass voltage corresponding to the pass voltage compensation signal; and a read voltage generator configured to output the read voltage corresponding to the read voltage compensation signal.
4. The device of claim 3 , wherein: at least one of the plurality of non-volatile memory cells has n threshold voltage levels; the second temperature compensation data are set at respective levels; and the compensator is configured to output the read voltage compensation signal in a sequence starting with the read voltage compensation signal corresponding to a first-level second temperature compensation data and ending with the read voltage compensation signal corresponding to an n-th-level second temperature compensation data.
5. The device of claim 3 , wherein: at least one of the plurality of non-volatile memory cells has n threshold voltage levels; the first temperature compensation data are set at first respective levels; and the second temperature compensation data are set at second respective levels; and the compensator is configured to output the pass voltage and the read voltage in a sequence starting with the pass voltage compensation signal corresponding to a first-level first temperature compensation data and the read voltage compensation signal corresponding to a first-level second temperature compensation data and ending with the pass voltage compensation signal corresponding to and n-th-level first temperature compensation data and the read voltage compensation signal corresponding to and n-th-level second temperature compensation data.
6. The device of claim 1 , wherein: at least one of the plurality of non-volatile memory cells has n threshold voltage levels; the temperature-compensated read voltage is a plurality of temperature-compensated read voltages; and the word line voltage application unit is configured to apply the temperature-compensated read voltages in a sequence starting with a temperature-compensated first-level read voltage and ending with a temperature-compensated n-th-level read voltage.
7. The device of claim 1 , wherein: at least one of the plurality of non-volatile memory cells has n threshold voltage levels; and the word line voltage application unit is configured to apply the temperature-compensated read voltage and the temperature-compensated pass voltage in a sequence starting with a temperature-compensated first-level read voltage and a temperature-compensated first-level pass voltage and ending with a temperature-compensated n-th-level read voltage and a temperature-compensated n-th-level pass voltage.
8. The device of claim 1 , wherein the memory cell array includes a NAND-type flash memory cell array.
9. A semiconductor memory device, comprising: a memory cell array comprising a plurality of word lines and a plurality of non-volatile memory cells connected to the plurality of word lines; and a word line voltage application unit configured to apply, in a first mode, a temperature-compensated read voltage to a selected word line of the plurality of word lines, and to apply, in a second mode during a read operation, the temperature-compensated read voltage to the selected word line of the plurality of word lines and a temperature-compensated pass voltage to at least one unselected word line of the plurality of word lines, wherein the first mode is a state in which an error detection rate of read data is less than a predetermined rate, and the second mode is a state in which the error detection rate of the read data is equal to or more than the predetermined rate.
10. The device of claim 9 , wherein the word line voltage application unit comprises: an error correction circuit configured to detect errors from the read data; a word line voltage generator configured to detect a temperature, to output, in the first mode, a temperature-compensated read voltage corresponding to the temperature, and to output, in the second mode, the temperature-compensated read voltage and a temperature-compensated pass voltage corresponding to the temperature; and a row decoder configured to apply the temperature-compensated read voltage to the selected word line, and to apply the temperature-compensated pass voltage to the at least one unselected word line.
11. The device of claim 9 , wherein: at least one of the plurality of non-volatile memory cells has n threshold voltage levels; and the word line voltage application unit is configured to apply, in the first mode, the temperature-compensated read voltage in a first sequence starting with a temperature-compensated first-level read voltage and ending with a temperature-compensated n-th-level read voltage.
12. The device of claim 11 , wherein the word line voltage application unit is configured to apply, in the second mode, the temperature-compensated read voltage in the first sequence.
13. The device of claim 11 , wherein the word line voltage application unit is configured to apply, in the second mode, the temperature-compensated read voltage in the first sequence and the temperature-compensated pass voltage in a second sequence starting with a temperature-compensated first-level pass voltage and ending with a temperature-compensated n-th-level pass voltage.
14. The device of claim 9 , wherein the memory cell array includes a NAND-type flash memory cell array.
15. A method of performing a read operation, the method comprising: applying, from a circuit during the read operation, a read voltage to a selected word line of a multi-level memory cell, wherein the read voltage is compensated for a temperature of the multi-level memory cell; and applying, from the circuit during the read operation, a pass voltage to at least one unselected word line of the multi-level memory cell, wherein the pass voltage is compensated for the temperature, wherein the applying the pass voltage comprises applying the pass voltage if a rate of error bits in data from the multi-level memory cell exceeds a predetermined rate.
16. The method as claimed in claim 15 , further comprising: producing, at the circuit, the read voltage from a temperature-compensated read voltage signal; producing, at the circuit, the temperature-compensated read voltage signal from first temperature compensation data corresponding to the temperature and a threshold voltage corresponding to the multi-level memory cell; producing, at the circuit, the pass voltage from a temperature-compensated pass voltage signal; and producing, at the circuit, the temperature-compensated pass voltage signal from second temperature compensation data corresponding to the temperature.
17. The method as claimed in claim 15 , wherein: the read voltage comprises a first read voltage corresponding to a first level of the multi-level memory cell and a second read voltage corresponding to a second level of the multi-level memory cell; and the applying the read voltage comprises applying, in a sequence, the first read voltage followed by the second read voltage.
18. The method as claimed in claim 17 , wherein: the pass voltage comprises a first pass voltage corresponding to the first level and a second pass voltage corresponding to the second level; and the applying the pass voltage comprises applying, in the sequence, the first pass voltage followed by the second pass voltage.
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October 21, 2013
April 7, 2015
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