Methods for forming semiconductor fins with reduced widths

1. A method comprising: forming Shallow Trench Isolation (STI) regions extending from a top surface of a semiconductor substrate into the semiconductor substrate; after the forming the STI regions, oxidizing an upper portion of a semiconductor strip between the STI regions, wherein a width of the upper portion of the semiconductor strip is reduced by the oxidizing, and wherein at a time the oxidizing the upper portion of the semiconductor strip is performed, top surfaces of the STI regions are higher than a top surface of the semiconductor strip; and recessing the STI regions, until a portion of the upper portion of the semiconductor strip is higher than a top surface of remaining portions of the STI regions to form a semiconductor fin.

2. The method of claim 1 , wherein at a time the oxidizing the upper portion of the semiconductor strip is performed, a pad oxide layer is located over the semiconductor strip.

3. The method of claim 2 further comprising, after the oxidizing the upper portion of the semiconductor strip is performed, removing the pad oxide layer and an oxide generated in the step of oxidizing.

4. The method of claim 1 , wherein the oxidizing the upper portion of the semiconductor strip is performed using In-Situ Steam Generation (ISSG), wherein a steam of water is generated by the ISSG, and wherein the upper portion of the semiconductor strip is oxidized by the steam.

5. The method of claim 1 further comprising: before the forming the STI regions, forming a patterned hard mask layer over the semiconductor strip; and after the forming the STI regions and before the oxidizing the upper portion of the semiconductor strip, removing the patterned hard mask layer.

6. The method of claim 1 , wherein in the oxidizing the upper portion of the semiconductor strip, a lower portion of the semiconductor strip is not oxidized.

7. The method of claim 1 further comprising: after the recessing the STI regions, forming a gate dielectric on a top surface and sidewalls of the semiconductor fin; and forming a gate electrode over the gate dielectric.

8. A method comprising: forming a patterned pad oxide layer over a semiconductor substrate; forming a patterned hard mask layer over the patterned pad oxide layer; etching the semiconductor substrate to form trenches in the semiconductor substrate, wherein the patterned pad oxide layer and the patterned hard mask layer are used as etching masks; filling the trenches with a dielectric material; removing excess portions of the dielectric material to form Shallow Trench Isolation (STI) regions in the trenches; removing the patterned hard mask layer; after the removing the patterned hard mask layer, oxidizing an upper portion of a semiconductor strip between the STI regions, wherein a width of the upper portion of the semiconductor strip is reduced; and after the oxidizing the upper portion of the semiconductor strip, removing the patterned pad oxide layer.

9. The method of claim 8 further comprising, after the oxidizing the upper portion of the semiconductor strip, recessing the STI regions, until a portion of the upper portion of the semiconductor strip is higher than a top surface of remaining portions of the STI regions to form a semiconductor fin.

10. The method of claim 9 further comprising: forming a gate dielectric on a top surface and sidewalls of the semiconductor fin; and forming a gate electrode over the gate dielectric.

11. The method of claim 8 , wherein the oxidizing the upper portion of the semiconductor strip is performed using In-Situ Steam Generation (ISSG), wherein a steam of water is generated by the ISSG, and wherein the upper portion of the semiconductor strip is oxidized by the steam.

12. The method of claim 8 , wherein in the oxidizing the upper portion of the semiconductor strip, a lower portion of the semiconductor strip is not oxidized.

13. The method of claim 12 , wherein the upper portion of the semiconductor strip has a height between about 2 percent and about 40 percent of a total height of the semiconductor strip.

14. A method comprising: forming Shallow Trench Isolation (STI) regions extending from a top surface of a semiconductor substrate into the semiconductor substrate, with a portion of the semiconductor substrate between two neighboring ones of the STI regions forming a semiconductor strip; after the forming the STI regions, thinning an upper portion of the semiconductor strip, wherein a lower portion of the semiconductor strip is not thinned; and after the thinning the upper portion of the semiconductor strip, recessing the STI regions, until a portion of the upper portion of the semiconductor strip is higher than top surfaces of remaining portions of the STI regions to form a semiconductor fin, wherein the top surfaces of the remaining portions of the STI regions are level with or higher than a bottom of the upper portion of the semiconductor strip.

15. The method of claim 14 , wherein at a time the thinning the upper portion of the semiconductor strip is performed, a pad oxide layer is located over the semiconductor strip.

16. The method of claim 14 , wherein the thinning the upper portion of the semiconductor strip comprises an oxidation of the upper portion of the semiconductor strip.

17. The method of claim 14 , wherein the thinning the upper portion of the semiconductor strip is performed using In-Situ Steam Generation (ISSG).

18. The method of claim 14 , wherein at a time the thinning the upper portion of the semiconductor strip is performed, top surfaces of the STI regions are higher than a top surface of the semiconductor strip.

19. The method of claim 14 further comprising: before the forming the STI regions, forming a hard mask layer over the semiconductor strip; and after the forming the STI regions and before the thinning the upper portion of the semiconductor strip, removing the hard mask layer.

20. The method of claim 14 , wherein the upper portion of the semiconductor strip has a height between about 2 percent and about 40 percent of a total height of the semiconductor strip.