Method and apparatus for switching power in a dual rail memory

1. A memory apparatus comprising: an array of bit cells arranged in rows and columns; a plurality of pairs of complementary bit lines, each column of the array being selectable by a corresponding pair of complementary bit lines; a plurality of power lines, each power line coupled to the bit cells in a corresponding column; and a plurality of voltage control circuits coupled to respective columns of the array, each voltage control circuit configured to set a voltage level of a respective one of the power lines responsive to logic levels of the pair of complementary bit lines corresponding to the respective column; wherein each voltage control circuit comprises: a NAND logic circuit including first and second input nodes coupled to the respective bit lines in the pair of bit lines corresponding to the respective column; a first PMOS transistor including a gate coupled to an output node of said NAND logic circuit, a source coupled to a power supply voltage, and a drain coupled to the power line corresponding to the respective column; a second PMOS transistor including a source coupled to the power supply voltage, a drain coupled to the power line corresponding to the respective column, and a gate coupled to the drain of said second PMOS transistor; a first NMOS transistor including a drain coupled to the power line corresponding to the respective column, and a gate coupled to the output node of said NAND logic circuit; a second NMOS transistor including a gate coupled to a first bit line in said pair of bit lines corresponding to the respective column, and a drain coupled to a source of said first NMOS transistor; a third NMOS transistor including a gate coupled to a second bit line in said pair of bit lines, and a drain coupled to the source of said first NMOS transistor; and a third PMOS transistor including a drain coupled to sources of said second and third NMOS transistors, a gate coupled to a ground node, and a source coupled to said ground node.

2. The memory apparatus of claim 1 , wherein said array of bit cells is a static random access memory (SRAM) array.

3. The memory apparatus of claim 1 , wherein each voltage control circuit is located adjacent to a bit cell at an end of the respective column.

4. The memory apparatus of claim 3 , wherein the plurality of voltage control circuits is a first plurality of voltage control circuits, the apparatus further comprising a second plurality of voltage control circuits coupled to respective columns of the array; wherein each voltage control circuit of the second plurality is configured to set the voltage level for a respective one of the power lines responsive to the logic levels of the pair of complementary bit lines corresponding to the respective column; wherein each voltage control circuit of the second plurality is disposed adjacent to a bit cell at another end of the respective column.

5. The memory apparatus of claim 3 , wherein the array of bit cells is a first array of bit cells, the apparatus further comprising a second array of bit cells arranged in rows and columns, the first and second arrays having a common number of columns, each column of the second array being selectable by a corresponding pair of complementary bit lines, each power line coupled to the bit cells of the second array in a corresponding column; wherein each voltage control circuit is coupled to a column of the second array, and the columns in the first and second arrays to which each voltage control circuit is coupled are the same; wherein each voltage control circuit is located adjacent to a bit cell of the second array at an end of the respective column.

6. The memory apparatus of claim 1 , wherein each voltage control circuit is configured to selectably provide, at a corresponding power line, first and second voltage levels for write and read operations, respectively, accessing said array of bit cells.

7. The memory apparatus of claim 6 , wherein each voltage control circuit is coupled to the power supply voltage, and the second voltage level is substantially equal to the power supply voltage.

8. A power supply configuration for a memory comprising: a NAND logic circuit including first and second input nodes and an output node; a first MOS transistor including a gate coupled to the output node of said NAND logic circuit, a source coupled to a power supply voltage, and a drain coupled to a power line, said first MOS transistor being a PMOS transistor; a second MOS transistor including a first terminal coupled to the power line, and a second terminal coupled to the power supply voltage; and a regulator circuit coupled to the output node of said NAND logic circuit and to the power line, said regulator circuit configured to regulate a characteristic of a voltage at the power line, based on a voltage at the output node of said NAND logic circuit, said regulator circuit including: a third MOS transistor including a drain coupled to the power line, and a gate coupled to the output node of said NAND logic circuit, said third MOS transistor being an NMOS transistor; a fourth MOS transistor including a gate coupled to one of the first and second input nodes of said NAND logic circuit, and a drain coupled to a source of said third MOS transistor, said fourth MOS transistor being an NMOS transistor; a fifth MOS transistor including a gate coupled to the other of the first and second input nodes, and a drain coupled to the source of said third MOS transistor, said fifth MOS transistor being an NMOS transistor; and a sixth MOS transistor including a drain coupled to sources of said fourth and fifth MOS transistors, a gate coupled to a ground node, and a source coupled to said ground node, said sixth MOS transistor being a PMOS transistor.

9. The apparatus of claim 8 , further comprising: an array of bit cells arranged in rows and columns; and first and second bit lines configured to select a corresponding column of the array; wherein the first and second input nodes of said NAND logic circuit are coupled to said first and second bit lines, respectively.

10. The memory apparatus of claim 8 , wherein said second MOS transistor is an NMOS transistor, and said first and second terminals are source and drain terminals, respectively, said second MOS transistor further including a gate coupled to the power supply voltage.

11. The memory apparatus of claim 8 , wherein said second MOS transistor is a PMOS transistor, and said first and second terminals are drain and source terminals, respectively, said second MOS transistor further including a gate coupled to the drain terminal of said second MOS transistor.

12. A memory apparatus comprising: an array of bit cells arranged in rows and columns; a plurality of pairs of complementary bit lines, each column of the array being selectable by a corresponding pair of complementary bit lines; a plurality of power lines, each power line coupled to the bit cells in a corresponding column; and a plurality of voltage control circuits coupled to respective columns of the array, each voltage control circuit configured to set a voltage level of a respective one of the power lines responsive to logic levels of the pair of complementary bit lines corresponding to the respective column; wherein each voltage control circuit comprises: a NAND logic circuit including first and second input nodes coupled to the respective bit lines in the pair of bit lines corresponding to the respective column; a first PMOS transistor including a gate coupled to an output node of said NAND logic circuit, a source coupled to a power supply voltage, and a drain coupled to the power line corresponding to the respective column; a first NMOS transistor including a drain coupled to the power line corresponding to the respective column, and a gate coupled to the output node of said NAND logic circuit; a second NMOS transistor including a gate coupled to a first bit line in said pair of bit lines corresponding to the respective column, and a drain coupled to a source of said first NMOS transistor; a third NMOS transistor including a gate coupled to a second bit line in said pair of bit lines, and a drain coupled to the source of said first NMOS transistor; and a second PMOS transistor including a drain coupled to sources of said second and third NMOS transistors, a gate coupled to a ground node, and a source coupled to said ground node.