In some embodiments, a method for manufacturing forms a semiconductor device, such as a transistor. A dielectric stack is formed on a semiconductor substrate. The stack comprises a plurality of dielectric layers separated by one of a plurality of spacer layers. Each of the plurality of spacer layers is formed of a different material than immediately neighboring layers of the plurality of dielectric layers. A vertically-extending hole is formed through the plurality of dielectric layers and the plurality of spacer layers. The hole is filled by performing an epitaxial deposition, with the material filling the hole forming a wire. The wire is doped and three of the dielectric layers are sequentially removed and replaced with conductive material, thereby forming upper and lower contacts to the wire and a gate between the upper and lower contacts. The wire may function as a channel region for a transistor.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for manufacturing a semiconductor device, comprising: providing a silicon substrate; forming a dielectric stack on the substrate, the dielectric stack comprising a plurality of dielectric layers, wherein neighboring dielectric layers are separated by a spacer layer formed of a different material than the neighboring dielectric layers; forming a vertically-extending hole through the dielectric stack; filling the hole by performing an epitaxial deposition, wherein material filling the hole forms a wire; forming a lateral etch stop, the lateral etch stop extending continuously around an area for accommodating the wire, wherein forming the lateral etch stops comprises: etching trenches through the dielectric stack and into the substrate; and at least partially filling the trenches with a material different from material forming the plurality of dielectric layers.
2. The method of claim 1 , wherein forming the dielectric stack comprises: forming a first spacer layer; forming a first dielectric layer; forming a second spacer layer; forming a second dielectric layer; forming a third spacer layer; forming a third dielectric layer; and forming a fourth spacer layer.
3. The method of claim 2 , further comprising: doping the first dielectric layer; and doping the third dielectric layer.
4. The method of claim 3 , further comprising diffusing dopant from the first and third dielectric layers to the wire.
5. The method of claim 4 , wherein diffusing dopant comprises annealing the dielectric stack to drive dopant from the first and third dielectric layers to the wire.
6. The method of claim 1 , wherein each of the plurality of dielectric layers comprises a same material.
7. The method of claim 6 , wherein each of the plurality of dielectric layers comprises silicon oxide.
8. The method of claim 1 , wherein each of the spacer layers comprises a same material.
9. The method of claim 8 , wherein each of the spacer layers comprises a silicon nitride.
10. The method of claim 1 , wherein forming the vertically-extending hole comprises etching the hole into the substrate.
11. The method of claim 1 , wherein filling the hole comprises doping material forming the wire as the material forming the wire is deposited.
12. The method of claim 1 , wherein filling the hole comprises depositing silicon, germanium, or combinations thereof.
13. The method of claim 1 , wherein a width of the wire is about 15 nm or less.
14. A method for manufacturing a semiconductor device, comprising: providing a silicon substrate; forming a dielectric stack on the substrate, the dielectric stack comprising a plurality of dielectric layers, wherein neighboring dielectric layers are separated by a spacer layer formed of a different material than the neighboring dielectric layers, wherein forming the dielectric stack comprises: depositing a first spacer layer; depositing a first dielectric layer; depositing a second spacer layer; depositing a second dielectric layer; depositing a third spacer layer; depositing a third dielectric layer; and depositing a fourth spacer layer; forming a vertically-extending hole through the dielectric stack; filling the hole by performing an epitaxial deposition, wherein material filling the hole forms a wire; and forming a lateral etch stop, the lateral etch stop extending continuously around an area for accommodating the wire, wherein forming the lateral etch stops comprises: etching trenches through the dielectric stack and into the substrate; and at least partially filling the trenches with a material different from material forming the plurality of dielectric layers.
15. The method of claim 14 , wherein forming the vertically-extending hole comprises forming a plurality of holes, and wherein filling the holes forms a plurality of the wires, each of the holes having one of the wires, and further comprising: forming a plurality of the lateral etch stops, the etch stops separating and delineating an array of areas, each area for accommodating one of the wires, wherein the plurality of lateral etch stops extend continuously around each area.
16. The method of claim 14 , further comprising: forming a first opening in the dielectric stack to expose the first dielectric layer; and selectively etching the first dielectric layer within an area surrounded by the lateral etch stop, thereby forming a first buried volume.
17. The method of claim 16 , further comprising filling the first buried volume with a lower conductive material, the lower conductive material electrically contacting the wire.
18. The method of claim 17 , further comprising: forming a second opening in the dielectric stack to expose the second dielectric layer; and selectively etching the second dielectric layer within the area surrounded by the lateral etch stop, thereby forming a second buried volume.
19. The method of claim 18 , further comprising forming a dielectric liner by depositing a high-k dielectric material in the second buried volume, including forming the dielectric liner on an exposed portion of the wire.
20. The method of claim 19 , further comprising filling the second buried volume with a middle conductive material, the middle conductive material disposed around a perimeter of the wire.
21. The method of claim 19 , wherein forming the dielectric liner comprises depositing the dielectric material by atomic layer deposition.
22. The method of claim 21 , further comprising: forming a third opening in the dielectric stack to expose the third dielectric layer; and selectively etching the third dielectric layer within the area surrounded by the lateral etch stop, thereby forming a third buried volume.
23. The method of claim 22 , further comprising filling the third buried volume with an upper conductive material, the upper conductive material electrically contacting the wire.
24. The method of claim 23 , wherein the wire forms a channel region of a transistor, wherein the lower conductive material forms a lower transistor contact, the middle conductive material forms a gate, and the upper conductive material forms an upper transistor contact.
25. The method of claim 24 , further comprising: forming a complementary wire in another area surrounded by the lateral etch stop, the another area being adjacent to the area in which the wire is accommodated.
26. The method of claim 25 , wherein upper and lower portions of the wire are P-doped, the wire forming a channel region of a PMOS transistor, and wherein upper and lower portions of the complementary wire are N-doped, the complementary wire forming a channel region of an NMOS transistor.
27. The method of claim 25 , wherein upper and lower portions of the wire and the complementary wire are oppositely doped, wherein the upper portion of the wire is oppositely doped relative to the upper portion of the complementary wire, and wherein the wire and complementary wire form complementary tunnel field-effect transistors.
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October 3, 2013
April 21, 2015
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