An electronic circuit includes a receiver circuit (BSP) operable to perform coherent summations having a coherent summations time interval, and a power control circuit (2130) coupled to said receiver circuit (BSP) and operable to impress a power controlling duty cycle (TON, TOFF) on the receiver circuit (BSP) inside the coherent summations time interval. Other circuits, devices, systems, methods of operation and processes of manufacture are also disclosed.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A power management circuit for controlling a process having a maximum available interval for coherent summations, the power management circuit comprising a power gating circuit operable to turn power on and off to at least one portion of the process; and a control circuit operable to establish a rate of turning the power on and off by said power gating circuit so that the rate equals or exceeds the reciprocal of the maximum available interval for coherent summations.
2. The power management circuit claimed in claim 1 wherein said power gating circuit is configurable and said control circuit is operable to configure said power gating circuit.
3. The power management circuit claimed in claim 2 wherein power is gated by at least part of said power gating circuit to said control circuit itself.
4. The power management circuit claimed in claim 1 wherein said control circuit is further operable to establish an on-time interval for said power gating circuit at the established rate.
5. The power management circuit claimed in claim 1 further comprising a voltage supply circuit operable to regulate power to said power gating circuit.
6. The power management circuit claimed in claim 1 wherein said control circuit has an input for at least one signal representing signal-to-noise ratio.
7. The power management circuit claimed in claim 1 wherein said control circuit has an input for at least one signal representing user application information.
8. The power management circuit claimed in claim 1 wherein said control circuit has an input for at least one signal representing Doppler difference.
9. The power management circuit claimed in claim 1 wherein said control circuit has an output for providing a signal representing a selected power save mode.
10. The power management circuit claimed in claim 1 wherein said control circuit has an output coupled to said power gating circuit for a power control signal at the established rate, and said control circuit is operable to turn the power control signal itself on and off at a second rate that is less than half the established rate of the power control signal.
11. The power management circuit claimed in claim 10 wherein said control circuit has an input for at least one signal representing Doppler difference and said control circuit is operable to adjust the second rate as a function of the Doppler difference.
12. The power management circuit claimed in claim 10 for use with a process also having noncoherent summations wherein said power gating circuit is responsive to said control circuit to gate power for the noncoherent summations at the second rate.
13. The power management circuit claimed in claim 1 wherein said control circuit includes a counter circuit feeding a decoder circuit.
14. The power management circuit claimed in claim 1 for use with an RF front-end process wherein said power gating circuit has a portion having a gated power output for the RF front-end process.
15. The power management circuit claimed in claim 1 for use with the process having channels wherein said power control circuit is operable to change a number of channels to be powered, and said power gating circuit is responsive to said power control circuit to gate power to the channels to be powered.
16. The power management circuit claimed in claim 1 wherein the process has plural portions and said power gating circuit is operable to turn power on and off to different portions at different times.
17. The power management circuit claimed in claim 1 wherein said control circuit is operable to enable the power control signal with an adjustable enable time that is at least twice the duration of the period of the established rate of the power control signal.
18. The power management circuit claimed in claim 17 wherein said control circuit has an input for a signal representative of a data decoding mode and said control circuit has a bypass to provide a continual enable for the power control signal during data decoding for the established rate to continue.
19. The power management circuit claimed in claim 1 wherein said control circuit has at least one input for signals representing a plurality of signal-to-noise ratios and said control circuit determines an off-time for the power control signal as a generally increasing function of at least one of the signal-to-noise ratios.
20. The power management circuit claimed in claim 1 wherein said control circuit has at least one input for signals representing a plurality of signal-to-noise ratios (SNRs) and said control circuit determines a duty cycle for the power control signal substantially according to the relationship 10^(−SNR extra /10), where extra signal-to-noise ratio SNR extra is in decibels (dB).
21. The power management circuit claimed in claim 1 wherein the process has symbol periods that are delayed relative to each other for the coherent summations in different channels.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 19, 2012
April 28, 2015
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