A semiconductor package has a substrate with a solder mask layer, and upper and lower surfaces. Conductive traces and electrical contacts are formed on the substrate, and vias are formed in the substrate to electrically connect the conductive traces and electrical contacts. A semiconductor die is attached on the upper surface of the substrate. A mold cap is formed on the upper surface of the substrate and covers the die and the conductive traces. The mold cap includes a mold body having clipped corners and extensions that extend from each of the clipped corners. The extensions and clipped corners help prevent package cracking.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor package, comprising: a substrate having an upper surface, a lower surface, and outer peripheral edges, wherein a plurality of conductive traces are formed on the upper surface of the substrate, a plurality of electrical contacts are formed on the lower surface of the substrate, and a plurality of vias are formed in the substrate to electrically connect the plurality of conductive traces and electrical contacts; a solder mask formed over and covering the substrate upper surface; a semiconductor die attached on the upper surface of the substrate; and a mold cap, formed on the upper surface of the substrate to cover the conductive traces, the semiconductor die, and at least part of the solder mask, wherein the mold cap includes, a mold body having chamfered corners, and a plurality of extensions respectively extending from each the chamfered corners, wherein the extensions extend from the chamfered corners towards the edges of the substrate and distal ends of the extensions are spaced from the substrate edges, wherein a height of the plurality of extensions is less than a height of the mold body.
2. The semiconductor package of claim 1 , wherein the plurality of extensions have a length that is about two-thirds the distance from the chamfered corners of the mold body to corresponding corners of the substrate.
3. The semiconductor package of claim 1 , wherein the plurality of extensions have a height that is about one-third the height of the mold body.
4. The semiconductor package of claim 1 , wherein the plurality of extensions are rectangular shaped and have a substantially flat upper surface.
5. The semiconductor package of claim 1 , wherein the plurality of extensions are formed together with the mold body.
6. The semiconductor package of claim 1 , wherein the electrical contacts comprise a plurality of conductive balls attached to the lower surface of the substrate.
7. The semiconductor package of claim 1 , wherein the sides of the mold body have a slope.
8. The semiconductor package of claim 1 , wherein the semiconductor die is electrically connected to the conductive traces of the substrate with bond wires.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 14, 2013
May 12, 2015
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