A single-ended low-swing power-savings mechanism is provided. The mechanism comprises a precharge device that turns off in an evaluation phase and a first biasing device is always on. Within the mechanism, a strength of a keeper device is changed to a first level in response to an input of the second biasing device being at a first voltage level. Within the mechanism the strength of the keeper device is changed to a second level in response to the input of the second biasing device being at a second voltage level. Responsive to receiving a (precharged voltage level read data line signal, a precharged voltage level of the first node falls faster when the keeper device is weakened to a first level. The keeper device turns on in response to receiving a LOW signal and pulls up the voltage at the first node so that a HIGH signal is output.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A single-ended low-swing power-savings mechanism, comprising: a precharge device coupled to a first biasing device, wherein the precharge device turns off in an evaluation phase and wherein the first biasing device is always on; a second biasing device coupled to a keeper device, wherein, responsive to an input of the second biasing device being at a first voltage level, a strength of the keeper device is changed to a first level, and wherein, responsive to the input of the second biasing device being at a second voltage level, the strength of the keeper device is changed to a second level; a first node coupled to the precharge device, the biasing device, the keeper device, and an input of an inverting amplifier, wherein, responsive to receiving a precharged voltage level read data line signal, precharged voltage level of the first node falls faster when the keeper device is weakened to a first level; and the keeper device coupled to an output of the inverting amplifier and a global bit line, wherein the keeper device turns on in response to receiving a LOW signal from the inverting amplifier and pulls up the voltage at the first node so that a HIGH signal is output onto a global data line.
2. The single-ended low-swing power-savings mechanism of claim 1 , wherein, responsive to the input of the second biasing device being at a first voltage level, the keeper device is weakened to a first level and wherein, responsive to an input of the second biasing device being at a second voltage level, the keeper device is weakened to a second level.
3. The single-ended low-swing power-savings mechanism of claim 2 , wherein the input of the second biasing device is received from a voltage-reference mechanism.
4. The single-ended low-swing power-savings mechanism of claim 3 , wherein the voltage-reference mechanism and the second biasing device together compensates across process variation.
5. The single-ended low-swing power-savings mechanism of claim 3 , wherein the voltage-reference mechanism and the second biasing device together enable operation across a wide process, voltage, and temperature (PVT) range.
6. The single-ended low-swing power-savings mechanism of claim 3 , wherein the voltage-reference mechanism comprises: a voltage divider coupled to a third biasing device, wherein, when the input to the voltage divider is LOW, the input to the second biasing device is at the first voltage level that causes the keeper device to weaken to the first level, and wherein, when an input to the voltage divider is HIGH, the input to the second biasing device is at the second voltage level that causes the keeper device to weaken to the second level.
7. The single-ended low-swing power-savings mechanism of claim 1 , wherein the keeper device turns off in response to receiving a HIGH signal from the inverting amplifier and pulls down the voltage at the first node so that a LOW signal is output onto the global data line.
8. The single-ended low-swing power-savings mechanism of claim 1 , wherein, in a precharge phase, the precharge device and the first biasing device precharges the read bit line and the first node to a lower voltage level than the supply voltage and wherein, by precharging the read bit line and the first node to the lower voltage level than the supply voltage, voltage swing is reduced during a read operation thereby reducing read power.
9. The single-ended low-swing power-savings mechanism of claim 1 , wherein a HIGH read data line signal indicates that a memory cell within a memory that is being read is storing a zero.
10. The single-ended low-swing power-savings mechanism of claim 1 , wherein the LOW read data line signal indicates that a memory cell within a memory that is being read is storing a one.
11. A memory comprising: a set of memory cells; and a single-ended low-swing power-savings mechanism coupled to the set of memory cells, wherein the single-ended low-swing power-savings mechanism comprises: a precharge device coupled to a first biasing device, wherein the precharge device turns off in an evaluation phase and wherein the first biasing device is always on; a second biasing device coupled to a keeper device, wherein, responsive to an input of the second biasing device being at a first voltage level, a strength of the keeper device is changed to a first level, and wherein, responsive to the input of the second biasing device being at a second voltage level, the strength of the keeper device is changed to a second level; a first node coupled to the precharge device, the biasing device, the keeper device, and an input of an inverting amplifier, wherein, responsive to receiving a precharged voltage level read data line signal, a precharged voltage level of the first node falls faster when the keeper device is weakened to a first level; and the keeper device coupled to an output of the inverting amplifier and a global bit line, wherein the keeper device turns on in response to receiving a LOW signal from the inverting amplifier and pulls up the voltage at the first node so that a HIGH signal is output onto a global data line.
12. The memory of claim 11 , wherein, responsive to the input of the second biasing device being at a first voltage level, the keeper device is weakened to a first level and wherein, responsive to an input of the second biasing device being at a second voltage level, the keeper device is weakened to a second level.
13. The memory of claim 12 , wherein the input of the second biasing device is received from a voltage-reference mechanism.
14. The memory of claim 13 , wherein the voltage-reference mechanism and the second biasing device together compensates across process variation.
15. The memory of claim 13 , wherein the voltage-reference mechanism and the second biasing device together enable operation across a wide process, voltage, and temperature (PVT) range.
16. The memory of claim 13 , wherein the voltage-reference mechanism comprises: a voltage divider coupled to a third biasing device, wherein, when the input to the voltage divider is LOW, the input to the second biasing device is at the first voltage level that causes the keeper device to weaken to the first level, and wherein, when an input to the voltage divider is HIGH, the input to the second biasing device is at the second voltage level that causes the keeper device to weaken to the second level.
17. The memory of claim 11 , wherein the keeper device turns off in response to receiving a HIGH signal from the inverting amplifier and pulls down the voltage at the first node so that a LOW signal is output onto the global data line.
18. The memory of claim 11 , wherein, in a precharge phase, the precharge device and the first biasing device precharges the read bit line and the first node to a lower voltage level than the supply voltage and wherein, by precharging the read bit line and the first node to the lower voltage level than the supply voltage, voltage swing is reduced during a read operation thereby reducing read power.
19. The memory of claim 11 , wherein a HIGH read data line signal indicates that a memory cell within a memory that is being read is storing a zero.
20. The memory of claim 11 , wherein the LOW read data line signal indicates that a memory cell within a memory that is being read is storing a one.
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July 26, 2013
June 2, 2015
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