The present disclosure includes apparatuses and methods for sensing a resistance variable memory cell. A number of embodiments include programming a memory cell to an initial data state and determining a data state of the memory cell by applying a programming signal to the memory cell, the programming signal associated with programming memory cells to a particular data state, and determining whether the data state of the memory cell changes from the initial data state to the particular data state during application of the programming signal.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus, comprising: an array of resistance variable memory cells; and a controller coupled to the array and configured to control: determining a data state of a memory cell by: applying a programming signal to the memory cell, the programming signal associated with programming memory cells to a particular data state; and determining whether the data state of the memory cell changes from an initial data state to the particular data state during application of the programming signal, by comparing a first sensed signal associated with the memory cell responsive to the applied programming signal to a second sensed signal associated with the memory cell responsive to the applied programming signal.
2. The apparatus of claim 1 , wherein determining the data state of the memory cell includes determining that the data state of the memory cell is the particular data when a difference between the first sensed signal and the second sensed signal is less than a threshold amount.
3. The apparatus of claim 1 , wherein determining the data state of the memory cell includes determining that the data state of the memory cell is a data state different from the particular data state when a difference between the first sensed signal and the second sensed signal is greater than or equal to a threshold amount.
4. The apparatus of claim 3 , wherein the data state of the memory cell is determined to be the data state different from the particular data state, the memory cell can be reprogrammed back to the initial state.
5. The apparatus of claim 1 , wherein determining whether the data state of the memory cell changes from the initial data state to the particular data state includes using a change determination component to determine a change in signal associated with the memory cell.
6. The apparatus of claim 5 , wherein determining the data state of the memory cell includes determining that the data state of the memory cell is the particular data state when the determined change in signal associated with the memory cell is less than a threshold amount.
7. The apparatus of claim 5 , wherein determining the data state of the memory cell includes determining that the data state of the memory cell is a data state different from the particular data state when the determined change in signal associated with the memory cell is greater than or equal to a threshold amount.
8. The apparatus of claim 5 , wherein the change determination component includes a diode, a capacitor, and a comparator.
9. The apparatus of claim 5 , wherein the change determination component includes a resistor, a capacitor, and a comparator.
10. An apparatus, comprising: an array of resistance variable memory cells; and a controller coupled to the array and configured to control: determining a data state of a memory cell by: applying a programming signal to the memory cell, the programming signal associated with programming memory cells to a particular data state; comparing a signal associated with the memory cell during a first time period while the programming signal is applied to the memory cell to a signal associated with the memory cell during a second time period while the programming signal is applied to the memory cell; and determining whether the data state of the memory cell changes from an initial data state to the particular data state during application of the programming signal.
11. The apparatus of claim 10 , wherein the controller is configured to control sensing the signal associated with the memory cell during the first time period and sensing the signal associated with the memory cell during the second time period.
12. The apparatus of claim 10 , wherein the controller is configured to determine the memory cell is in the particular data state if the signal associated with the memory cell during the first time period is different than the signal associated with the memory cell during the second time period by less than a threshold amount.
13. The apparatus of claim 10 , wherein the controller is configured to determine the memory cell is in a data state different from the particular data state if the signal associated with the memory cell during the first time period is different than the signal associated with the memory cell during the second time period by greater than or equal to a threshold amount.
14. The apparatus of claim 13 , wherein the controller is configured to control applying a programming signal associated with programming memory cells to the data state different from the particular data state when the signal associated with the memory cell during the first time period is different than the signal associated with the memory cell during the second time period by greater than or equal to a threshold amount.
15. The apparatus of claim 10 , wherein comparing the signal associated with the memory cell during the first time period to the signal associated with the memory cell during the second time period includes using a change determination component.
16. The apparatus of claim 10 , wherein the change determination component includes a first capacitor, a second capacitor, and a comparator.
17. An apparatus, comprising: an array of resistance variable memory cells; and a controller coupled to the array and configured to control: determining a data state of a memory cell by: applying a programming signal to the memory cell, the programming signal associated with programming memory cells to a particular data state; sensing a first signal associated with the memory cell while the programming signal is applied to the memory cell; and determining a change in the first signal associated with the memory cell by comparing the first signal to a second signal associated with the memory cell while the programming signal is applied to the memory cell.
18. The apparatus of claim 17 , comprising a change determination component that determines the change in the signal associated with the memory cell while the programming signal is applied to the memory cell.
19. The apparatus of claim 17 , wherein the controller is configured to determine that the memory cell is in the particular data state if the change in the first signal associated with the memory cell is less than a threshold amount.
20. The apparatus of claim 17 , wherein the controller is configured to determine that the memory cell is in a different data state than the particular data state if the change in the first signal associated with the memory cell is greater than or equal to a threshold amount.
21. The apparatus of claim 20 , wherein the controller is configured to control applying a programming signal associated with programming memory cells to the data state different from the particular data state when the change in the first signal associated with the memory cell determined is greater than or equal to a threshold amount.
22. The apparatus of claim 17 , wherein the controller is configured to apply the programming signal by ramping the programming signal through a range of signals associated with programming memory cells to the particular data state.
23. The apparatus of claim 17 , wherein sensing the first signal associated with the memory cell comprises sensing a sense line associated with the memory cell.
24. A method for sensing a resistance variable memory cell, comprising: applying a programming signal to a memory cell, the programming signal associated with programming memory cells to a particular data state; sensing a signal associated with the memory cell while the programming signal is being applied to the memory during a first time period; sensing a signal associated with the memory cell while the programming signal is being applied to the memory during a second time period; and determining whether a data state of the memory cell changes from an initial data state to the particular data state during application of the programming signal by comparing the signals sensed during the first time period and during the second time period.
25. The method of claim 24 , wherein determining whether the data state of the memory cell changes from an initial data state to the particular data state includes determining that the data state of the memory cell is the particular data state if application of the programming signal changes the data state of the memory cell from the initial data state to the particular data state and determining that the data state of the memory cell is different from the particular data state if application of the programming signal does not change the data state of the memory cell from the initial data state to the particular data state.
26. The method of claim 24 , wherein the method includes programming the memory cell from the particular data state back to the initial data state if it is determined that application of the programming signal changed the data state of the memory cell from the initial data state to the particular data state.
27. The method of claim 24 , wherein the method includes determining whether the data state of the memory cell changes via a controller coupled to the memory cell.
28. The method of claim 24 , wherein applying the programming signal includes applying a programming ramp signal to the memory cell.
29. The method of claim 24 , wherein determining whether the data state of the memory cell changes from the initial data state to the particular data state during application of the programming signal by comparing the signals sensed during the first time period and during the second time period includes determining a change in the slope of an electrical characteristic between the signal sensed during the first time period and the signal sensed during the second time period.
30. A method for sensing a resistance variable memory cell, comprising: applying a programming signal to a memory cell, wherein the programming signal is associated with programming memory cells to a particular data state, and wherein the memory cell has been previously programmed to an initial data state; sensing a first signal associated with the memory cell while the programming signal is applied to the memory cell; sensing a second signal associated with the memory cell while the programming signal is applied to the memory cell; and determining whether a data state of the memory cell changes to the particular data state from a data state different from the particular data state by comparing the first sensed signal to the second sensed signal.
31. The method of claim 30 , wherein the method includes determining the memory cell is in the particular data state if the first sensed signal is different from the second sensed signal by less than a threshold amount.
32. The method of claim 31 , wherein the method includes leaving the memory cell in the particular data state when the memory cell is determined to be in the particular data state if the first sensed signal is different from the second sensed signal by less than a threshold amount.
33. The method of claim 30 wherein the method includes determining the memory cell is in the data state different from the particular data state if the first sensed signal is different from the second sensed signal by greater than or equal to a threshold amount.
34. The method of claim 33 , wherein the method includes programming the memory cell back to the initial data state if the memory cell is determined to be in the different data state.
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April 24, 2013
June 2, 2015
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