The system for offsetting the input voltage unbalance in multilevel inverters or the like comprises a control unit operatively associated with a multilevel inverter for converting direct current into alternate current, the control unit being suitable for piloting the multilevel inverter for generating an output current depending on a reference current, and an equalization unit for equalizing the input voltages of the multilevel inverter having first generation means of a harmonic component of order equal to the reference current, out of phase with respect to the fundamental component of the reference current, detection means of the unbalance of the input voltages to the multilevel inverter, regulation means of the amplitude of the harmonic component depending on the detected unbalance, for offsetting the unbalance. The method for offsetting the unbalance of the input voltages in multilevel inverters or the like comprises a control phase of a multilevel inverter for converting direct current into alternate current, in which the multilevel inverter is piloted for generating an output current depending on a reference current, a generation phase of a harmonic component of order equal to the reference current, out of phase with respect to the fundamental component of the reference current, a detection phase of the unbalance of the input voltages to the multilevel inverter and a regulation phase of the amplitude of the harmonic component depending on the detected unbalance, for offsetting the unbalance.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A system (O) for offsetting an input voltage unbalance in multilevel inverters, comprising at least a control unit (U) operatively associated with at least a multilevel inverter (I) for converting direct current into alternate current, said control unit (U) controlling said multilevel inverter (I) for generating at least an output current (I out ) depending on at least a reference current (I ref ), and at least an equalization unit (E) for equalizing input voltages (V bus+ , V bus− ) of said multilevel inverter (I) having: first generation means (G1) of at least a harmonic component (I ehj ) of order equal to said reference current (I ref ), out of phase with respect to a fundamental component (I fund ) of said reference current (I ref ); detection means (D) of the unbalance of the input voltages (V bus+ , V bus− ) to said multilevel inverter (I); regulation means (R) of an amplitude (|I ehj |) of said harmonic component (I ehj ) depending on the detected unbalance of the input voltages (V bus+ , V bus− ) to said multilevel inverter (I), for offsetting said unbalance of the input voltages (V bus+ , V bus− ) to said multilevel inverter (I); wherein said equalization unit (E) comprises at least an adding device (A) associated with said first generation means (G1) adding said harmonic component (I ehj ) to said fundamental component (I fund ) to obtain said reference current (I ref ).
2. The system (O) according to claim 1 , wherein said detection means (D) of the unbalance of the input voltages (V bus+ , V bus− ) to said multilevel inverter (I) are associated with at least an input branch (B) to said multilevel inverter (I) having at least two capacitors (C bus+ , C bus− ) serially connected, at least a terminal associated with a positive pole (V dc +) of a power voltage source (PW) and at least an opposite terminal associated with a negative pole (V dc− ) of said power voltage source (PW), said input voltages (V bus+ , V bus− ) to said multilevel inverter (I) being made up of voltages at the heads of said capacitors (C bus+ , C bus− ).
3. The system (O) according to claim 2 , wherein said detection means (D) of the unbalance of the input voltages (V bus+ , V bus− ) to said multilevel inverter (I) are associated with said input branch (B) and with said regulation means (R) and comprise at least a calculation device (D) calculating a difference between said input voltages (V bus+ , V bus− ) to said multilevel inverter (I).
4. The system (O) according to claim 1 , wherein said control unit (U) comprises generation means for generating control signals (P a , P b , P c , P d ) modulated by pulse width depending on said reference current (I ref ), controlling at least a first, a second, a third and a fourth switch (S a , S b , S c , S d ) of said multilevel inverter (I) for the generation of said output current (I out ).
5. The system (O) according to claim 1 , wherein said harmonic component (I ehj ) is a second order harmonic.
6. The system (O) according to claim 5 , wherein an out-of-phase angle of said harmonic component (I ehj ) with respect to said fundamental component (I fund ) is equal to 90*+k*1800, with k equal to any whole number.
7. The system (O) according to claim 1 , comprising second generation means (G2) of said fundamental component (I fund ) of the reference current (I ref ).
8. The system (O) according to claim 1 , wherein said fundamental component (I fund ) of the reference current (I ref ) is in phase with a mains voltage (V grid ) injected on a power distribution network (G) downstream of said multilevel inverter (I).
9. The system (O) according to claim 1 , comprising at least a synchronization device (PH) associated with said first generation means (G1), determining the phase (θ fund ) of said fundamental component (I fund ) starting with a phase of the mains voltage (V grid ) injected on a power distribution network (G) downstream of said multilevel inverter (I).
10. The system (O) according to claim 7 , comprising at least a synchronization device (PH) associated with said second generation means (G2), determining the phase (θ ehj ) of said harmonic component (I ehj ) with respect to said fundamental component (I fund ).
11. A method for offsetting the unbalance of input voltages (V bus+ , V bus− ) in multilevel inverters (I), comprising the following steps: providing a control stage of at least a multilevel inverter (I) for converting direct current into alternate current, in which said multilevel inverter (I) is controlled for generating at least an output current (I out ) depending on at least a reference current (I ref ); generating at least a harmonic component (I ehj ) of order equal to said reference current (I ref ), out of phase with respect to a fundamental component (I fund ) of said reference current (I ref ); detecting the unbalance of the input voltages (V bus+ , V bus− ) to said multilevel inverter (I); regulating an amplitude (|I ehj |) of said harmonic component (I ehj ) depending on the detected unbalance of the input voltages (V bus+ , V bus− ) to said multilevel inverter (I), for offsetting said unbalance of the input voltages (V bus+ , V bus− ) to said multilevel inverter (I); and adding said harmonic component (I ehj ) and said fundamental component (I fund ) to obtain said reference current (I ref ).
12. The method according to claim 11 , wherein said detection step of the unbalance of the input voltages (V bus+ , V bus− ) to said multilevel inverter (I) is performed on at least an input branch (B) to said multilevel inverter (I) having at least two capacitors (C bus+ , C bus− ) serially connected, at least a terminal associated with a positive pole (V dc +) of a power voltage source (PW) and at least an opposite terminal associated with a negative pole (V dc− ) of said power voltage source (PW), said input voltages (V bus+ , V bus− ) to said multilevel inverter (I) being made up of voltages at the heads of said capacitors (C bus+ , C bus− ).
13. The method according to claim 12 , wherein said detection step of the unbalance of the input voltages (V bus+ , V bus− ) to said multilevel inverter (I) comprises the calculation of a difference between said input voltages (V bus+ , V bus− ) to said multilevel inverter (I).
14. The method according to claim 11 , wherein said control comprises the generation of control signals (P a , P b , P c , P d ) modulated by pulse width depending on said reference current (I ref ), controlling at least a first, a second, a third and a fourth switch (S a , S b , S c , S d ) of said multilevel inverter (I) for the generation of said output current (I out ).
15. The method according to claim 11 , wherein said harmonic component (I ehj ) is a second order harmonic.
16. The method according to claim 11 , comprising at least a determination stage of a displacement between said fundamental component (I fund ) and harmonic component (I ehj ) of the reference current (I ref ).
17. The method according to claim 11 , wherein an out-of-phase angle of said harmonic component (I ehj ) with respect to said fundamental component (I fund ) is equal to 90*+k*1800, with k equal to any whole number.
18. The method according to claim 11 , comprising at least a generation stage of said fundamental component (I fund ) of the reference current (I ref ).
19. The method according to claim 11 , wherein said fundamental component (I fund ) of the reference current (I ref ) is in phase with a mains voltage (V grid ) injected on a power distribution network (G) downstream of said multilevel inverter (I).
20. The method according to claim 11 , comprising at least a synchronization stage of the phase of said fundamental component (I fund ) of the reference current (I ref ) with the phase of the mains voltage (V grid ) injected on a power distribution network (G) downstream of said multilevel inverter (I).
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 12, 2010
June 2, 2015
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.