A method and structure are disclosed for increasing strain in a device, specifically an n-type field effect transistor (NFET) complementary metal-oxide-semiconductor (CMOS) device. Embodiments of this invention include an n-type field effect transistor (NFET) complementary metal-oxide-semiconductor (CMOS) device having a source region and a drain region, the NFET CMOS including: an n-type doped layer in at least one of the source region and the drain region, wherein the n-type doped layer includes substitutional carbon and has a memorized tensile stress induced by a stress memorization technique (SMT).
Legal claims defining the scope of protection, as filed with the USPTO.
1. An n-type field effect transistor (NFET) complementary metal-oxide-semiconductor (CMOS) device having a source region and a drain region, the NFET CMOS comprising: an n-type doped layer in at least one of the source region and the drain region, wherein the n-type doped layer includes a lower portion and an upper portion, wherein the lower portion includes substitutional carbon and has a memorized tensile stress induced by a stress memorization technique (SMT), and wherein the upper portion includes an implantation layer including silicon carbon phosphorus (SiCP) with an additional n-type dopant; and a lower n-type doped layer, positioned under the n-typed doped layer, wherein the lower n-type doped layer comprises crystalline silicon carbon phosphorous (SiCP), wherein the lower n-type doped layer and the lower portion of the n-type doped layer are separated by an intermediate layer, wherein the intermediate layer comprises n-type doped silicon (Si), and wherein the intermediate layer has a thickness of approximately 5 nm.
2. The NFET CMOS of claim 1 , wherein the additional n-type dopant comprises a dopant selected from the group consisting of: phosphorus (P), antimony (Sb) and arsenic (As).
3. The NFET CMOS of claim 1 , wherein the lower n-type doped layer and the n-type doped layer both have a thickness of approximately 20 to approximately 50 nm.
4. An n-type field effect transistor (NFET) complementary metal-oxide-semiconductor (CMOS) device having a source region and a drain region, the NFET CMOS comprising: an n-type doped layer in at least one of the source region and the drain region, wherein the n-type doped layer includes a lower portion and an upper portion, wherein the lower portion includes substitutional carbon and has a memorized tensile stress induced by a stress memorization technique (SMT), and wherein the upper portion includes an implantation layer including silicon carbon phosphorous (SiCP) with an additional n-type dopant; and a lower n-type doped layer, positioned under the n-typed doped layer, wherein the lower n-type doped layer comprises crystalline silicon carbon phosphorous (SiCP), wherein the lower n-type doped layer and the lower portion of the n-type doped layer both have a thickness of approximately 20 to approximately 50 nm.
5. The NFET CMOS of claim 4 , wherein the lower n-type doped layer and the n-type doped layer are separated by an intermediate layer, wherein the intermediate layer comprises n-type doped silicon (Si).
6. The NFET CMOS of claim 5 , wherein the intermediate layer has a thickness of approximately 5 nm.
7. The NFET CMOS of claim 4 , wherein the additional n-type dopant comprises a dopant selected from the group consisting of: phosphorus (P), antimony (Sb) and arsenic (As).
8. An n-type field effect transistor (NFET) complementary metal-oxide-semiconductor (CMOS) device having a source region and a drain region, the NFET CMOS comprising: an n-type doped layer in at least one of the source region and the drain region, wherein the n-type doped layer includes a lower portion and an upper portion, wherein the lower portion includes substitutional carbon and has a memorized tensile stress induced by a stress memorization technique (SMT), and wherein the upper portion includes an implantation layer within the n-type doped layer, wherein the implantation layer comprises silicon carbon phosphorous (SiCP) with an additional n-type dopant, wherein the additional n-type dopant comprises a dopant selected from the group consisting of: phosphorus (P), antimony (Sb) and arsenic (As); and a lower n-type doped layer, positioned under the n-typed doped layer, wherein the lower n-type doped layer comprises crystalline silicon carbon phosphorous (SiCP), wherein the lower n-type doped layer and the lower portion of the n-type doped layer are separated by an intermediate layer, wherein the intermediate layer comprises n-type doped silicon (Si).
9. The NFET CMOS of claim 8 , wherein the intermediate layer has a thickness of approximately 5 nm.
10. The NFET CMOS of claim 8 , wherein the lower n-type doped layer and the n-type doped layer both have a thickness of approximately 20 to approximately 50 nm.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 20, 2013
June 16, 2015
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