Architecture for VBUS pulsing in an Ultra Deep Sub Micron (UDSM) process for ensuring USB-OTG (On The Go) session request protocol, the architecture being of the type wherein at least a charging circuit is deployed, uses a diode-means connected in a forward path of the charging circuit. The architecture might include a diode-divider including nodes and connected from VBUS in said charging circuit. One embodiment uses both charging and discharging circuits comprising transistors. The charging circuit transistor might comprise a PMOS transistor and the discharging circuit transistor might comprise a NMOS transistor. The architecture might include a three resistance string of a total resistance value approximating 100K Ohms connected between said VBUS and ground, wherein the discharging circuit transistor might comprise a drain extended NMOS transistor. The charging and discharging circuit transistors have VDS and VGD of about 3.6V, whereby high VGS transistors are not needed.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus, comprising: a first switch directly coupled to a reference voltage; a first resistor coupling ground to said first switch; a diode directly coupling said first switch to a VBUS; a second resistor coupling said first switch to a second switch, said second switch being further directly coupled to ground; and a third resistor coupling said second switch to said VBUS.
2. The apparatus of claim 1 , wherein said reference voltage is 3.3V.
3. The apparatus of claim 1 , wherein pulsing of said VBUS is enabled by driving the VBUS to an intermediate voltage for a session request protocol in a USB (Universal Serial Bus)-OTG (On The Go) application.
4. The apparatus of claim 1 , wherein said diode, first switch and second switch are implemented using an ultra-deep sub-micron (UDSM) process.
5. The apparatus of claim 1 , wherein said first switch and said second switch are transistors.
6. The apparatus of claim 1 , wherein said first switch is a charging transistor and said second switch is a discharging transistor.
7. The apparatus of claim 6 , wherein said charging and discharging transistors are MOS transistors.
8. The apparatus of claim 7 , wherein said charging transistor comprises a PMOS transistor and said discharging transistor comprises an NMOS transistor.
9. The apparatus of claim 6 , wherein the charging and discharging transistors have a maximum VDS and VGD of 3.6V.
10. A method, comprising: coupling a first switch directly to a reference voltage; coupling ground to said first switch via a first resistor; coupling said first switch to a VBUS via a diode; coupling said first switch to a second switch via a second resistor, said second switch being further directly coupled to ground; and coupling said second switch to said VBUS via a third resistor.
11. The method of claim 10 , wherein said reference voltage is 3.3V.
12. The method of claim 10 , wherein pulsing of said VBUS is enabled by driving the VBUS to an intermediate voltage for a session request protocol in a USB (Universal Serial Bus)-OTG (On The Go) application.
13. The method of claim 10 , wherein said diode, first switch and second switch are implemented using an ultra-deep sub-micron (UDSM) process.
14. The method of claim 13 , wherein said first switch and said second switch are transistors.
15. The method of claim 14 , wherein said first switch is a charging transistor and said second switch is a discharging transistor.
16. The method of claim 15 , wherein said charging and discharging transistors are MOS transistors.
17. The method of claim 16 , wherein said charging transistor comprises a PMOS transistor and said discharging transistor comprises an NMOS transistor.
18. The method of claim 14 , wherein the charging and discharging transistors have a maximum VDS and VGD of 3.6V.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 22, 2014
June 23, 2015
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