The present disclosure includes methods and devices for parallel encryption/decryption. In one or more embodiments, an encryption/decryption device includes an input logic circuit, an output logic circuit, and a number of encryption/decryption circuits arranged in parallel between the input logic circuit and the output logic circuit. For example, each encryption/decryption circuit can be capable of processing data at an encryption/decryption rate, and the number of encryption/decryption circuits can be equal to or greater than an interface throughput rate divided by the encryption/decryption rate.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An encryption/decryption device, comprising an input logic circuit configured to parse data into a number of groups; an output logic circuit; and a number of encryption/decryption circuits arranged in parallel between the input logic circuit and the output logic circuit, each encryption/decryption circuit being capable of processing data at an encryption/decryption rate, wherein the input logic circuit is configured to distribute one group of the number of groups per each selection of a particular encryption/decryption circuit of the number of encryption/decryption circuits in a round robin sequence, wherein the round robin sequence excludes at least one of the number of encryption/decryption circuits to accommodate a rate at which data is received by the encryption/decryption device; and wherein the number of encryption/decryption circuits are configured to increment first initialization vectors for subsequent use as second initialization vectors.
2. The encryption/decryption device of claim 1 , wherein the number of parallel encryption/decryption circuits is equal to or greater than a host interface throughput rate divided by the encryption/decryption rate.
3. The encryption/decryption device of claim 1 , wherein the input logic circuit operates to parse an input data stream into a number of groups, and distribute the number of groups to at least some of the number of parallel encryption/decryption circuits according to a distribution order.
4. The encryption/decryption device of claim 1 , wherein the number of parallel encryption/decryption circuits operate to process the group of data according to an advanced encryption/decryption standard algorithm in a cipher block chaining mode.
5. The encryption/decryption device of claim 1 , wherein engines of the number of parallel encryption/decryption circuits are configured to receive a key, and wherein a key received by one of the encryption/decryption engines is different than a key received by another one of the encryption/decryption engines.
6. The encryption/decryption device of claim 1 , wherein engines of the number of parallel encryption/decryption circuits are configured to receive a key, and wherein each encryption/decryption engine is configured to receive a same key as another encryption/decryption engine.
7. The encryption/decryption device of claim 1 , wherein at least one encryption/decryption circuit is capable of processing data at a respective encryption/decryption rate that is substantially different from another one of the number of encryption/decryption circuits.
8. A method, comprising parsing an input data stream received at a host interface into a number of groups; and distributing the number of groups in a distribution order among a number of parallel encryption/decryption circuits having an encryption/decryption circuit data processing rate; and using incremented previously-used initialization vectors by the number of parallel encryption/decryption circuits; operating the number of parallel encryption/decryption circuits in an electronic codebook mode, wherein distributing the number of groups includes one group being distributed per each selection of a particular encryption/decryption circuit in a round robin sequence, wherein the round robin sequence excludes at least one of the number of parallel encryption/decryption circuits to accommodate a rate at which the input data stream is received at the host interface.
9. The method of claim 8 , further comprising: combining initialization vectors with a first number of groups to each of the number of parallel encryption/decryption circuits; and combining an encrypted output of each of the number of parallel encryption/decryption circuits with a second number of groups to each of the number of parallel encryption/decryption circuits.
10. The method of claim 8 , wherein the number of parallel encryption/decryption circuits is at least a maximum throughput rate of the host interface divided by the data processing rate.
11. The method of claim 8 , wherein using incremented previously-used initialization vectors includes incrementing initialization vectors of one of the number of parallel encryption/decryption circuits for subsequent use as initialization vectors of another one of the number of parallel encryption/decryption circuits.
12. A method, comprising parsing, via a hardware interface, an input data stream into a number of groups, the input data stream having a first rate; and distributing the number of groups in a round robin sequence among 3 of 4 parallel encryption/decryption circuits operating in an electronic codebook mode, one group being distributed per each selection of a particular encryption/decryption circuit in the round robin sequence; and processing a particular group at a time through one of the 3 of 4 parallel encryption/decryption circuits at a data processing rate, wherein the 3 of 4 parallel encryption/decryption circuits accommodate the first rate, and wherein the first rate is at most 3 times an uppermost throughput rate of the hardware interface divided by the data processing rate.
13. The method of claim 12 , wherein the data processing rate is an encryption/decryption rate.
14. The method of claim 12 , wherein the encryption/decryption circuit implements an Advanced Encryption Standard (AES) algorithm in electronic code book mode.
15. The method of claim 12 , wherein initialization vectors are combined with a first number of groups to each parallel encryption/decryption circuit, and an encrypted output of each respective parallel encryption/decryption circuit is combined with a second number of groups to each respective parallel encryption/decryption circuit.
16. The method of claim 12 , wherein initialization vectors are combined with a first group to each parallel encryption/decryption circuit, and an encrypted output from a preceding group of each parallel encryption/decryption circuit is combined with a succeeding group to each respective parallel encryption/decryption circuit.
17. The method of claim 12 , including: incrementing initialization vectors for a first parallel encryption/decryption circuit; and using the incremented initialization vectors as initialization vectors for a second parallel encryption/decryption circuit.
18. The method of claim 12 , wherein: distributing one of the number of groups to an encryption/decryption circuit takes T clock cycles; and processing one of the number of groups at a time through an encryption/decryption circuit takes 3T clock cycles.
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January 15, 2013
June 23, 2015
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