An addressable node unit includes connections for at least two lines via which the node unit can be addressed. The connections are connected to a circuit which evaluates an addressing signal. The node unit includes at least one power source which is supplyable with power via at least one of the lines. A switch is provided in the path between the evaluating circuit and the corresponding line connection, the switch being opened after an addressing process so that the power supply of the evaluating circuit is ensured by the at least one power source after the addressing.
Legal claims defining the scope of protection, as filed with the USPTO.
1. Addressable node unit comprising: a first and a second connection for at least a first and a second line, through which the node unit is addressable, said connections being connected to an evaluating circuit useable to evaluate an addressing signal, wherein a first switch is associated with the first connection and a second switch is associated with the second connection, wherein the first and the second switch are arranged so as to establish, in a closed state thereof, an electrical connection between the first and the second connections, the switches being by-passed by respective diodes with a cathode in common between the at least first and second lines so that a signal flow is possible in two directions; and at least one current source, supplyable with current through at least one of the at least first and second lines, wherein a further switch is connected to the cathode, in common with the two diodes, between the evaluating circuit and a corresponding one of the first and second connections, the further switch being opened after addressing so that current supply to the evaluating circuit is ensured, after addressing, by the at least one current source and data thereafter is exchangeable between the evaluating circuit and the node unit.
2. The addressable node unit of claim 1 , wherein the evaluating circuit comprises two components, one of the two components being designed as a synchronous logic which disposes of a clock signal of a clock generator, and the other of the two component comprising asynchronous functions and its own supply network, separate from that of the synchronous logic component, which includes diodes and a storage element and obtains its supply directly from the at least first and second lines, wherein a charge is obtainable from the at least first and second lines if a voltage between the at least first and second lines is relatively higher than that in the storage element.
3. The addressable node unit of claim 1 , wherein the further switch, connected to the cathodes in common of the two diodes, is a transistor switch.
4. The addressable node unit of claim 3 , wherein the transistor switch is a metal-oxide-semiconductor field effect (MOSFET) transistor.
5. The addressable node unit of claim 1 , wherein the addressable node unit is formed with two signal sensors for signals from two different directions.
6. The addressable node unit of claim 5 , wherein at least one of the evaluating circuit is formed with at least one control output for switching over the direction of at least one of transmitting and receiving; and the evaluating circuit is provided with a transistor with a respective collector line for each one of the directions for emitting signals in both directions.
7. The method of claim 6 , wherein, for passing addressing from one of the at least two node units to another of the at least two node units, each of the at least two node units comprises, apart from the further switch, a first and a second switch by-passed by diodes with a cathode in common, wherein the further switch is connected to the cathode in common, and wherein actuation of the first and second switches for charging at least one current storage is effected in a time-delayed manner.
8. The addressable node unit of claim 1 , further comprising: at least one signal sensor, permanently connected to the at least first and second lines independently from said further switch.
9. The addressable node unit of claim 1 , wherein the first and second switches by-pass an unaddressed node.
10. The addressable node unit of claim 1 , wherein the at least one current source is isolated from the first line and the second line when the further switch is open.
11. A method for addressing at least two node units via at least one controller, the method comprising: emitting a first addressing signal, via the at least one controller, to a first node unit of the at least two node units, the first addressing signal being delivered to an evaluating circuit connected to the first node unit; interrupting passage of the first addressing signal to a second node unit of the at least two node units; emitting, via the controller, a second addressing signal which is different from the first addressing signal, subsequent to the interrupting, by which connection is made to a respective next node unit of the at least two node units, the interrupting of passage of the first addressing signal to the evaluating circuit connected to the first node unit being achieved via a switch, opened after addressing such that the first addressing signal of the controller subsequently addresses the second node unit, connection between the controller and the evaluating circuit connected to the first node unit being reestablishable for subsequent addressing via a reset signal; and interrupting addressing of the respective next node unit, via a further switch connected to cathodes in common with two diodes between the evaluating circuit and corresponding line connections.
12. The method of claim 11 , wherein at least the first addressing signal is a voltage signal.
13. The method of claim 12 , wherein the second addressing signal is a voltage signal, and wherein amplitudes of the first and second addressing signals are different.
14. The method of claim 13 , wherein, for passing addressing from one of the at least two node units to another of the at least two node units, each of the at least two node units comprises, apart from the further switch, a first and a second switch by-passed by diodes with a cathode in common, wherein the further switch is connected to the cathode in common, and wherein actuation of the first and second switches for charging at least one current storage is effected in a time-delayed manner.
15. The method of claim 12 , wherein, for passing addressing from one of the at least two node units to another of the at least two node units, each of the at least two node units comprises, apart from the further switch, a first and a second switch by-passed by diodes with a cathode in common, wherein the further switch is connected to the cathode in common, and wherein actuation of the first and second switches for charging at least one current storage is effected in a time-delayed manner.
16. The method of claim 11 , wherein a current of the first addressing signal is supplied to at least one current storage for charging the first addressing signal.
17. The method of claim 16 , wherein, for passing addressing from one of the at least two node units to another of the at least two node units, each of the at least two node units comprises, apart from the further switch, a first and a second switch by-passed by diodes with a cathode in common, wherein the further switch is connected to the cathode in common, and wherein actuation of the first and second switches for charging at least one current storage is effected in a time-delayed manner.
18. The method of claim 11 , wherein, for passing addressing from one of the at least two node units to another of the at least two node units, each of the at least two node units comprises, apart from the further switch, a first and a second switch by-passed by diodes with a cathode in common, wherein the further switch is connected to the cathode in common, and wherein actuation of the first and second additional switches for charging at least one current storage is effected in a time-delayed manner.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 25, 2011
June 23, 2015
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