Semiconductor device

1. A semiconductor device comprising first and second bank groups coupled to first and second data lines which are electrically isolated from each other, the semiconductor device comprising: a register unit suitable for providing predetermined data to the second data line in a specific mode; a data transfer and output unit suitable for externally outputting the predetermined data loaded onto the second data line and simultaneously transferring the predetermined data to the first data line in the specific mode; and a data output unit suitable for externally outputting the predetermined data loaded onto the first data line in the specific mode, wherein the specific mode comprises a maximum data width option mode of data width option modes supported by the semiconductor device and a multi-purpose register (MPR) operation mode.

2. The semiconductor device of claim 1 , wherein the register unit is disposed in a second peripheral area closer to a second memory area in which the second bank group is disposed than to a first memory area in which the first bank group is disposed, and the data transfer and output unit and the data output unit are disposed in a first peripheral area closer to the first memory area than to the second memory area.

3. The semiconductor device of claim 1 , wherein the register unit comprises a multi-purpose register (MPR).

4. The semiconductor device of claim 1 , wherein the data output unit externally outputs first normal data of the first bank group loaded onto the first data line in a normal mode, and the data transfer and output unit externally outputs second normal data of the second bank group loaded onto the second data line in the normal mode.

5. A semiconductor device comprising first and second bank groups coupled to first and second data lines which are electrically isolated from each other, the semiconductor device comprising: a multi-purpose register (MPR) suitable for providing multi-purpose data to the second data line in response to an MPR mode signal; a route selection unit suitable for generating first and second route selection signals by combining first and second bank group selection signals, the MPR mode signal, and a predetermined data width option mode signal; a route providing and data output unit suitable for externally outputting the multi-purpose data loaded onto the second data line and simultaneously transferring the multi-purpose data to the first data line in response to the first and the second route selection signals; and a data output unit suitable for externally outputting the multi-purpose data loaded onto the first data line in response to the first route selection signal.

6. The semiconductor device of claim 5 , wherein: the multi-purpose register is disposed in a second peripheral area closer to a second memory area in which the second bank group is disposed than to a first memory area in which the first bank group is disposed, and the route providing and data output unit and the data output unit are disposed in a first peripheral area closer to the first memory area than to the second memory area.

7. The semiconductor device of claim 5 , wherein: the data output unit externally outputs normal data of the first bank group loaded onto the first data line in a normal mode, and the route providing and the data output unit externally outputs normal data of the second bank group loaded onto the second data line in the normal mode.

8. The semiconductor device of claim 7 , wherein the data output unit comprises: a first route connection unit suitable for selectively coupling the first data line to a first coupling node in response to the first route selection signal; a first pipe latch unit suitable for temporarily storing data transferred through the first coupling node; and a first output unit suitable for externally outputting the data latched in the first pipe latch unit.

9. The semiconductor device of claim 7 , wherein the route providing and the data output unit comprises: a second route connection unit suitable for coupling at least one of the first and the second data lines to a second coupling node in response to the first and the second route selection signals; a second pipe latch unit suitable for temporarily storing data transferred through the second coupling node; and a second output unit suitable for externally outputting the data latched in the second pipe latch unit.

10. The semiconductor device of claim 5 , wherein the predetermined data width option mode signal is a signal corresponding to a maximum data width option mode of data width option modes supported by the semiconductor device.

11. A semiconductor device comprising first and second bank groups coupled to first and second data lines which are electrically isolated from each other, the semiconductor device, the semiconductor device comprising: a multi-purpose register (MPR) suitable for providing multi-purpose data to the first data line in response to an MPR mode signal; an enable signal generation unit suitable for generating an enable signal in response to an MPR mode signal and a predetermined data width option mode signal; a driver suitable for transferring the multi-purpose data loaded onto the first data line to the second data line in response to the enable signal; a first data output unit suitable for externally outputting the multi-purpose data loaded onto the first data line; and a second data output unit suitable for externally outputting the multi-purpose data loaded onto the second data line.

12. The semiconductor device of claim 11 , wherein the multi-purpose register is disposed in a first peripheral area closer to a first memory area in which the first bank group is disposed than to a second memory area in which the second bank group is disposed, and the first and the second data output unit is disposed in a second peripheral area closer to the second memory area than to the first memory area.

13. The semiconductor device of claim 11 , wherein the first data output unit externally outputs normal data of the first bank group loaded onto the first data line in a normal mode, and the second data output unit externally outputs normal data of the second bank group loaded onto the second data line in the normal mode.

14. The semiconductor device of claim 11 , wherein the predetermined data width option mode signal is a signal corresponding to a maximum data width option mode of data width option modes supported by the semiconductor device.