One method disclosed herein includes forming an etch stop layer above recessed sidewall spacers and a recessed replacement gate structure and, with the etch stop layer in position, forming a self-aligned contact that is conductively coupled to the source/drain region after forming the self-aligned contact. A device disclosed herein includes an etch stop layer that is positioned above a recessed replacement gate structure and recessed sidewall spacers, wherein the etch stop layer defines an etch stop recess that contains a layer of insulating material positioned therein. The device further includes a self-aligned contact.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of forming a transistor, comprising: forming a replacement gate structure that is positioned within a gate cavity that is laterally defined by sidewall spacers positioned in a first layer of insulating material; performing at least one etching process to recess said sidewall spacers and said replacement gate structure and thereby define recessed sidewall spacers and a recessed replacement gate structure, wherein an upper surface of said recessed sidewall spacers is positioned above an upper surface of said recessed replacement gate structure; forming an etch stop layer above said recessed sidewall spacers and said recessed replacement gate structure, said etch stop layer defining an etch stop recess; forming a second layer of insulating material in said etch stop recess; forming a third layer of insulating material above said second layer of insulating material and above said etch stop layer; with said etch stop layer in position, performing at least one first contact etching process to form a self-aligned contact opening that extends through at least said third layer of insulating material and said first layer of insulating material and thereby exposes a source/drain region of said transistor; and with said etch stop layer in position, forming a self-aligned contact in said self-aligned contact opening that is conductively coupled to said source/drain region.
2. The method of claim 1 , wherein said etch stop layer is comprised of a high-k insulating material.
3. The method of claim 1 , wherein performing said at least one etching process to recess said sidewall spacers and said replacement gate structure comprises: performing at least one first etching process to recess said sidewall spacers; and after performing said at least one first etching process, performing at least one second etching process to recess said replacement gate structure.
4. The method of claim 1 , wherein performing said at least one etching process to recess said sidewall spacers and said replacement gate structure comprises: performing at least one first etching process to recess said replacement gate structure; and after performing said at least one first etching process, performing at least one second etching process to recess said sidewall spacers.
5. The method of claim 1 , wherein, after performing said at least one etching process and prior to forming said etch stop layer, the method further comprises selectively forming a fourth layer of insulating material on an upper surface of said recessed replacement gate structure.
6. The method of claim 5 , wherein an upper surface of said fourth layer of insulating material is positioned level with or below an upper surface of said recessed sidewall spacers.
7. The method of claim 1 , wherein forming said second layer of insulating material in said etch stop recess comprises: depositing said second layer of insulating material above said etch stop layer so as to over-fill said etch stop recess; and performing at least one planarization process to remove portions of said second layer of insulating material and portions of said etch stop layer positioned above an upper surface of said first layer of insulating material.
8. The method of claim 1 , wherein, prior to forming said self-aligned contact, the method comprises performing an etching process to remove portions of said etch stop layer exposed when forming said self-aligned contact opening.
9. The method of claim 1 , wherein, during performing said at least one first contact etching process to form said self-aligned contact opening, at least a portion of said second layer of insulating material positioned within said etch stop recess is removed and at least a portion of said etch stop layer is exposed.
10. The method of claim 1 , wherein said at least one first contact etching process to form said self-aligned contact opening is performed for a sufficient duration so as to intentionally remove portions of said etch stop liner and said recessed sidewall spacers and thereby increase a size of said contact opening.
11. A method of forming a transistor, comprising: forming a replacement gate structure that is positioned within a gate cavity that is laterally defined by sidewall spacers positioned in a first layer of insulating material; performing at least one etching process to recess said sidewall spacers and said replacement gate structure and thereby define recessed sidewall spacers and a recessed replacement gate structure; selectively forming a second layer of insulating material on an upper surface of said recessed replacement gate structure; forming an etch stop layer comprised of high-k insulating material above said recessed sidewall spacers, said recessed replacement gate structure, said second layer of insulating material and above an upper surface of said first layer of insulating material, said etch stop layer defining an etch stop recess; forming a third layer of insulating material in said etch stop recess by: depositing said third layer of insulating material above said etch stop layer so as to over-fill said etch stop recess; and performing at least one planarization process to remove portions of said third layer of insulating material and portions of said etch stop layer positioned above said upper surface of said first layer of insulating material; forming a fourth layer of insulating material above said third layer of insulating material and above said etch stop layer; with said etch stop layer in position, performing at least one first contact etching process to form a self-aligned contact opening that extends through at least said fourth layer of insulating material and said first layer of insulating material and thereby exposes a source/drain region of said transistor; and with said etch stop layer in position, forming a self-aligned contact in said self-aligned contact opening that is conductively coupled to said source/drain region.
12. The method of claim 11 , wherein performing said at least one etching process to recess said sidewall spacers and said replacement gate structure comprises: performing at least one first etching process to recess said sidewall spacers; and after performing said at least one first etching process, performing at least one second etching process to recess said replacement gate structure.
13. The method of claim 11 , wherein performing said at least one etching process to recess said sidewall spacers and said replacement gate structure comprises: performing at least one first etching process to recess said replacement gate structure; and after performing said at least one first etching process, performing at least one second etching process to recess said sidewall spacers.
14. The method of claim 11 , wherein an upper surface of said recessed sidewall spacers is positioned above an upper surface of said recessed replacement gate structure.
15. The method of claim 14 , wherein an upper surface of said second layer of insulating material is positioned level with or below said upper surface of said recessed sidewall spacers.
16. The method of claim 11 , wherein, selectively forming said second layer of insulating material on said upper surface of said recessed replacement gate structure comprises performing a selective self-assembly process.
17. The method of claim 11 , wherein said at least one first contact etching process to form said self-aligned contact opening is performed for a sufficient duration so as to intentionally remove portions of said etch stop liner and said recessed sidewall spacers and thereby increase a size of said contact opening.
18. The method of claim 11 , wherein, prior to forming said self-aligned contact, the method comprises performing an etching process to remove portions of said etch stop layer exposed when forming said self-aligned contact opening.
19. A method of forming a transistor, comprising: forming a replacement gate structure that is positioned within a gate cavity that is laterally defined by sidewall spacers positioned in a first layer of insulating material; performing at least one etching process to recess said sidewall spacers and said replacement gate structure and thereby define recessed sidewall spacers and a recessed replacement gate structure; after performing said at least one etching process, selectively forming a second layer of insulating material on an upper surface of said recessed replacement gate structure, wherein an upper surface of said second layer of insulating material is positioned level with or below an upper surface of said recessed sidewall spacers; after selectively forming said second layer of insulating material, forming an etch stop layer above said recessed sidewall spacers and said recessed replacement gate structure, said etch stop layer defining an etch stop recess; forming a third layer of insulating material in said etch stop recess; forming a fourth layer of insulating material above said third layer of insulating material and above said etch stop layer; with said etch stop layer in position, performing at least one first contact etching process to form a self-aligned contact opening that extends through at least said fourth layer of insulating material and said first layer of insulating material and thereby exposes a source/drain region of said transistor; and with said etch stop layer in position, forming a self-aligned contact in said self-aligned contact opening that is conductively coupled to said source/drain region.
20. A method of forming a transistor, comprising: forming a replacement gate structure that is positioned within a gate cavity that is laterally defined by sidewall spacers positioned in a first layer of insulating material; performing at least one etching process to recess said sidewall spacers and said replacement gate structure and thereby define recessed sidewall spacers and a recessed replacement gate structure; forming an etch stop layer above said recessed sidewall spacers and said recessed replacement gate structure, said etch stop layer defining an etch stop recess; forming a second layer of insulating material in said etch stop recess, wherein forming said second layer of insulating material in said etch stop recess comprises: depositing said second layer of insulating material above said etch stop layer so as to over-fill said etch stop recess; and performing at least one planarization process to remove portions of said second layer of insulating material and portions of said etch stop layer positioned above an upper surface of said first layer of insulating material; forming a third layer of insulating material above said second layer of insulating material and above said etch stop layer; with said etch stop layer in position, performing at least one first contact etching process to form a self-aligned contact opening that extends through at least said third layer of insulating material and said first layer of insulating material and thereby exposes a source/drain region of said transistor; and with said etch stop layer in position, forming a self-aligned contact in said self-aligned contact opening that is conductively coupled to said source/drain region.
21. A method of forming a transistor, comprising: forming a replacement gate structure that is positioned within a gate cavity that is laterally defined by sidewall spacers positioned in a first layer of insulating material; performing at least one etching process to recess said sidewall spacers and said replacement gate structure and thereby define recessed sidewall spacers and a recessed replacement gate structure; forming an etch stop layer above said recessed sidewall spacers and said recessed replacement gate structure, said etch stop layer defining an etch stop recess; forming a second layer of insulating material in said etch stop recess; forming a third layer of insulating material above said second layer of insulating material and above said etch stop layer; with said etch stop layer in position, performing at least one first contact etching process to form a self-aligned contact opening that extends through at least said third layer of insulating material and said first layer of insulating material and thereby exposes a source/drain region of said transistor; performing an etching process to remove portions of said etch stop layer exposed when forming said self-aligned contact opening; and with said etch stop layer in position, forming a self-aligned contact in said self-aligned contact opening that is conductively coupled to said source/drain region.
22. A method of forming a transistor, comprising: forming a replacement gate structure that is positioned within a gate cavity that is laterally defined by sidewall spacers positioned in a first layer of insulating material; performing at least one etching process to recess said sidewall spacers and said replacement gate structure and thereby define recessed sidewall spacers and a recessed replacement gate structure; forming an etch stop layer above said recessed sidewall spacers and said recessed replacement gate structure, said etch stop layer defining an etch stop recess; forming a second layer of insulating material in said etch stop recess; forming a third layer of insulating material above said second layer of insulating material and above said etch stop layer; with said etch stop layer in position, performing at least one first contact etching process to form a self-aligned contact opening that extends through at least said third layer of insulating material and said first layer of insulating material and thereby exposes a source/drain region of said transistor; wherein, during performing said at least one first contact etching process to form said self-aligned contact opening, at least a portion of said second layer of insulating material positioned within said etch stop recess is removed and at least a portion of said etch stop layer is exposed; and with said etch stop layer in position, forming a self-aligned contact in said self-aligned contact opening that is conductively coupled to said source/drain region.
23. A method of forming a transistor, comprising: forming a replacement gate structure that is positioned within a gate cavity that is laterally defined by sidewall spacers positioned in a first layer of insulating material; performing at least one etching process to recess said sidewall spacers and said replacement gate structure and thereby define recessed sidewall spacers and a recessed replacement gate structure; forming an etch stop layer above said recessed sidewall spacers and said recessed replacement gate structure, said etch stop layer defining an etch stop recess; forming a second layer of insulating material in said etch stop recess; forming a third layer of insulating material above said second layer of insulating material and above said etch stop layer; with said etch stop layer in position, performing at least one first contact etching process to form a self-aligned contact opening that extends through at least said third layer of insulating material and said first layer of insulating material and thereby exposes a source/drain region of said transistor, wherein said at least one first contact etching process to form said self-aligned contact opening is performed for a sufficient duration so as to intentionally remove portions of said etch stop liner and said recessed sidewall spacers and thereby increase a size of said contact opening; and with said etch stop layer in position, forming a self-aligned contact in said self-aligned contact opening that is conductively coupled to said source/drain region.
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August 2, 2013
June 30, 2015
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