Apparatuses and methods for adjusting deactivation voltages are described herein. An example apparatus may include a voltage control circuit. The voltage control circuit may be configured to receive an address and to adjust a deactivation voltage of an access line associated with a target group of memory cells from a first voltage to a second voltage based, at least in part, on the address. In some examples, the first voltage may be lower than the second voltage.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus, comprising: a voltage control circuit configured to receive an address associate target group of memory cells, the voltage control circuit further configured to, during an access of the target group of memory cells; provide an activation voltage to a first access line that is associated with the address to activate the target group of memory cells; provide a first deactivation voltage to the first access line after the target group of memory cell is activated, wherein the deactivation voltage is less than the activation voltage; and provide a second deactivation voltage to a second access line that is physically adjacent to the first access line and coupled to another group of memory cells, wherein the first deactivation voltage is greater than the second deactivation voltage.
2. The apparatus of claim 1 , wherein the voltage control circuit is further configured to provide the second deactivation voltage to the first access line a period of time after provision of the first deactivation voltage to the access line.
3. The apparatus of claim 1 , wherein the voltage control first deactivation voltage control circuit is further configured to provide the first deactivation voltage to a bus while the first access line is activated.
4. The apparatus of claim 1 , wherein the first access line, the second access line, and a third access line physically adjacent the first access line are each coupled to respective drivers, each of the respective drivers coupled to the voltage control circuit by a separate bus.
5. The apparatus of claim 1 , wherein the voltage control circuit is configured to provide the first deactivation voltage during a refresh operation.
6. The apparatus of claim 1 , wherein the apparatus is included in a memory.
7. The apparatus of claim 1 , wherein the access line comprises a word line.
8. The apparatus of claim 1 , wherein the group of memory cells comprises a row of memory cells.
9. An apparatus, comprising: a first access line associated with a target group of memory cells; a second access line associated with another group of memory cells; a voltage control circuit coupled to a first driver and a second driver, the voltage control circuit configured to provide a first deactivation voltage to the first driver to deactivate the target group of memory cells and to provide a second deactivation voltage to the second driver to deactivate the another group of memory cells, wherein the second deactivation voltage is lower than the first deactivation voltage.
10. The apparatus of claim 9 , wherein at least one of the first driver or the second driver comprises an inverter pair.
11. The apparatus of claim 9 , wherein the first driver is coupled to the voltage control circuit by a first bus and the second driver is coupled to the voltage control circuit by a second bus.
12. The apparatus of claim 9 , wherein the voltage control circuit is further configured to provide the second deactivation voltage to the first driver after providing the first deactivation voltage to the first driver for a period of time.
13. The apparatus of claim 9 , wherein the second access line is physically adjacent the first access line.
14. The apparatus of claim 9 , wherein the voltage control circuit is further configured to generate the first and second deactivation voltages.
15. The apparatus of claim 9 , wherein the group of memory cells comprises a row of memory cells.
16. An apparatus, comprising: a first plurality of drivers coupled to a first plurality of access lines respectively; a second plurality of drivers coupled to a second plurality of access lines respectively; a voltage control circuit coupled to the first plurality of drivers by a first bus and coupled to the second plurality of drivers by a second bus, the voltage control circuit configured to provide a first deactivation voltage to the first plurality of drivers to deactivate memory cells coupled to the first plurality of access lines and second plurality of drivers to deactivate memory cells coupled to the second plurality of access lines, the voltage control circuit further configured to provide a second deactivation voltage based, at least in part, on an address associated with an access line of the first plurality of access lines, wherein the first deactivation voltage is lower than the second deactivation voltage.
17. The apparatus of claim 16 , wherein the second plurality of access lines comprises an access line that is physically adjacent the access line of the first plurality of access lines.
18. A method, comprising: providing, with a driver, a first deactivation voltage to an access line coupled to a target group of memory cells for a first portion of a memory operation; providing, with the driver, an activation voltage to the access line for a second portion of the memory operation; to activate the target group of memory cells; providing, with the driver, a second deactivation voltage to the access line for a third portion of the memory operation, the first deactivation voltage lower than the second deactivation voltage; and providing the first deactivation voltage to at least one access line physically adjacent to the access line during the memory operation.
19. The method of claim 18 , further comprising: after providing the second deactivation voltage to the access line, providing, with the driver, the first deactivation voltage to the access line.
20. The method of claim 19 , wherein said providing, with the driver, the first deactivation voltage to the access line comprises providing, with the driver, the first deactivation voltage to the access line after providing the second deactivation voltage to the access line.
21. The method of claim 18 , wherein the access line is associated with the target group of memory cells that is repeatedly accessed.
22. A method, comprising: during a memory operation, adjusting the deactivation voltage of a first plurality of access lines from a first voltage to a second voltage, wherein the deactivation voltage is configured to deactivate a first group of memory cells coupled to the first plurality of access lines, wherein the first voltage is less than the second voltage; and during the memory operation, maintaining the deactivation voltage of a second plurality of access lines at the first voltage, wherein the deactivation voltage is configured to deactivate a second group of memory cells coupled to the second plurality of access lines.
23. The method of claim 22 , wherein the first plurality of access lines includes an access line associated with a target group of memory cells of the memory operation.
24. The method of claim 22 , wherein the second plurality of access lines includes first and second access lines physically adjacent an access line associated with a target group of memory cells.
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July 23, 2013
July 14, 2015
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