Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a package substrate having first and second major surfaces. The package substrate includes a base substrate having a mold material and a plurality of interconnect structures including via contacts extending through the first to the second major surface of the package substrate. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structures. A cap is formed over the package substrate to encapsulate the die.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for forming a semiconductor package comprising: providing a package substrate having first and second major surfaces, wherein the package substrate comprises a base substrate having a mold material and a plurality of interconnect structures including via contacts extending through the first to the second major surface of the package substrate, wherein providing the package substrate comprises providing a conductive carrier having first, second and third conductive layers, wherein the first conductive layer is patterned to define a pattern which defines the via contacts of the package substrate and a plurality of cavities and the second conductive layer serves as an etch stop layer while patterning the first conductive layer, and wherein the via contact comprises a width defined by circumference of the via contact; and filling the cavities with the mold material to form the base substrate of the package substrate; forming further interconnect level of the package substrate which comprises forming a plurality of conductive studs directly coupled to and contact the via contacts by patterning the second and third conductive layers of the same conductive carrier, wherein a width of the conductive stud which is defined by circumference of the conductive stud is smaller than the width of the via contacts and the conductive stud is formed and contained within and does not extend beyond the width of the via contact; providing a die having conductive contacts on its first or second surface, wherein the conductive contacts of the die are electrically coupled to the interconnect structures; and forming a cap over the package substrate to encapsulate the die.
2. The method of claim 1 comprising forming conductive traces which are coupled to and contacts the conductive studs having materials of the second and third conductive layers, wherein the via contacts, conductive studs and conductive traces form the interconnect structures.
3. The method of claim 2 wherein the conductive traces are formed by plating.
4. The method of claim 3 wherein the conductive traces extends from under the die to periphery region of the die.
5. The method of claim 1 comprising providing a dielectric layer in direct contact with and partially covers the via contacts.
6. The method of claim 1 wherein the conductive studs are formed at peripheries of the package substrate such that side surfaces of the conductive studs are exposed.
7. The method of claim 1 wherein the first conductive layer is patterned by a mask and an etch to remove portions of the first conductive layer unprotected by the mask.
8. The method of claim 1 wherein: excessive mold material is formed above a top surface of the via contact; and comprising removing excessive mold material from one surface of the conductive carrier such that top surfaces of the via contacts are exposed.
9. The method of claim 1 wherein the cavities are filled by the mold material by transfer molding, printing, film assisted molding or compression molding technique.
10. The method of claim 1 wherein the conductive stud is formed at the center of the via contact.
11. The method of claim 1 wherein: the second and third conductive layers are formed by plating; and the second conductive layer comprises a material which is different than materials of the first and third conductive layers.
12. The method of claim 11 wherein the second conductive layer comprises nickel and the first and third conductive layers comprise copper.
13. The method of claim 1 wherein patterning the second and third conductive layers comprises first and second etch processes.
14. The method of claim 13 wherein the first etch process removes portions of the third conductive layer and stops on the second conductive layer and the second etch process removes portions of the second conductive layer and stops at a surface defined by top surfaces of the via contacts and the mold material.
15. The method of claim 1 comprising providing an insulating layer which covers and fills spaces between the conductive studs, wherein the insulating layer also partially covers and contacts top surface of the via contacts.
16. The method of claim 15 comprising forming conductive traces which are directly coupled to and extend from side surfaces of the conductive studs.
17. The method of claim 16 wherein the conductive traces are formed directly over top surface of the insulating layer.
18. The method of claim 17 wherein the conductive traces extend from the side surfaces of the conductive studs and beyond the width of the conductive studs.
19. The method of claim 18 wherein the cap directly contacts top surface of the conductive traces.
20. The method of claim 15 wherein top surface of the conductive studs is flushed with top surface of the insulating layer.
21. The method of claim 20 wherein the insulating layer and the mold material comprise different dielectric materials.
22. The method of claim 21 wherein the insulating layer comprises solder mask or inorganic insulating film and the mold material comprises epoxy resin material.
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March 14, 2013
July 21, 2015
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