Disclosed is a memory including a plurality of resistive change memory cells, including at least a first group and a second group of the memory cells and a comparison circuit configured to conduct a direct relative comparison of a remaining endurance of the first group of memory cells to a remaining endurance of the second group of memory cells.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method comprising: selecting a first group of memory cells in a memory; while the first group of memory cells are in a predetermined test state, measuring a first metric indicative of a remaining endurance of the first group of memory cells; selecting a second group of memory cells in the memory; while the second group of memory cells are in the predetermined test state, measuring a second metric indicative of a remaining endurance of the second group of memory cells; comparing the first and second metrics; and forming a result responsive to the comparing step.
2. The method of claim 1 wherein the test state is a high resistance state.
3. The method of claim 2 wherein the first and second metrics are measured concurrently.
4. The method of claim 2 wherein the first and second metrics are measured sequentially.
5. The method of claim 2 wherein measuring the first and second metrics comprises directly measuring at least one respective current in each of the first and second groups of memory cells.
6. The method of claim 2 wherein measuring at least one respective current comprises measuring bit line currents, word line currents, global bit line currents or source line currents in each of the first and second groups of memory cells.
7. The method of claim 2 wherein the result comprises a binary swap signal, the swap signal having a first state indicating that the first group of memory cells has a relatively better remaining endurance than the second group of memory cells, and a second state indicating that the second group of memory cells has a relatively better remaining endurance than the first group of memory cells.
8. The method of claim 2 and further comprising utilizing the result for identifying one of the groups of memory cells as a target for a write operation.
9. The method of claim 2 and further comprising utilizing the result for selecting one of the groups of memory cells for a subsequent wear leveling action.
10. The method of claim 2 and further comprising utilizing the result for selecting one of the groups of memory cells for re-location of data during a refresh operation.
11. The method of claim 1 and further comprising: based on the result of the comparison, swapping an order of the first and second groups of memory cells in a listing of the groups; and repeating the comparing and swapping steps so as to complete a bubble sort of the list of groups into an order based on estimated remaining endurance.
12. The method of claim 1 wherein the resistive memory cells comprise conductive bridge resistive RAM (CB-RRAM) cells.
13. The method of claim 1 wherein the resistive memory cells comprise phase change resistive RAM (PCRAM) cells.
14. The method of claim 1 wherein the resistive memory cells comprise interfacial resistive RAM.
15. The method of claim 1 wherein the resistive memory cells comprise resistive RAM that requires a forming step.
16. The method of claim 1 wherein the comparison circuit is arranged to compare respective currents flowing through the first and second groups of memory cells to generate the comparison result.
17. A memory controller comprising: a request interface for receiving memory access requests; a memory interface for interconnecting the memory controller with a memory having at least one array of resistive change memory cells; and an address mapping circuit; wherein the address mapping circuit implements address mapping responsive at least in part to direct relative measurement of a selected remaining endurance metric among different groups of memory cells in the memory.
18. The memory controller of claim 17 wherein the memory controller is coupled to a current comparator circuit to obtain direct relative measurement of respective currents flowing through first and second groups of cells in the memory.
19. The memory controller of claim 17 including evaluation logic configured to realize the direct relative measurement of remaining endurance among different groups of memory cells in the memory.
20. The memory controller of claim 17 wherein the controller is configured to receive a result of direct relative measurement of respective currents flowing through first and second groups of memory cells resulting from an evaluation operation in the memory.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 7, 2013
August 18, 2015
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