A non-volatile memory of an embodiment includes a plurality of memory cells, each of the memory cells including a plurality of transistors including a first to fourth transistors, a first non-volatile element, a second non-volatile element, a first node, and a second node, the first and second transistors being connected in series with the first non-volatile element, the third and fourth transistors being connected in series with the second non-volatile element, the first node being disposed between the first and second transistors, the second node being disposed between the third and fourth transistors, gates of the first and third transistors being connected to one of first wiring lines, a gate of the second transistor being connected to the second node, a gate of the fourth transistor being connected to the first node, the first transistor being connected between one of second wiring lines and the first node.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A non-volatile memory comprising: a plurality of memory cells arranged in a matrix form; a plurality of first wiring lines each corresponding to memory cells of a common row; a plurality of second wiring lines and a plurality of third wiring lines, each of the plurality of second wiring lines corresponding to memory cells of a common column, each of the plurality of third wiring lines corresponding to memory cells of the common column; and a plurality of fourth wiring lines and fifth wiring lines, each of the plurality of fourth wiring lines and fifth wiring lines corresponding to the memory cells of one of the common row and the common column; each of the memory cells including a plurality of transistors, a first non-volatile element, a second non-volatile element, a first node, and a second node, the transistors including a first transistor, a second transistor, a third transistor, and a fourth transistor, the first transistor and the second transistor being connected in series with the first non-volatile element, the third transistor and the fourth transistor being connected in series with the second non-volatile element, the first node being disposed between the first transistor and the second transistor, the second node being disposed between the third transistor and the fourth transistor, gates of the first transistor and the third transistor being connected to one of the first wiring lines, a gate of the second transistor being connected to the second node, a gate of the fourth transistor being connected to the first node, the first transistor being connected between one of the second wiring lines and the first node, the second transistor being connected between the first node and one of the fourth wiring lines, the third transistor being connected between one of the third wiring lines and the second node, the fourth transistor being connected between the second node and the one of the fifth wiring lines, the first non-volatile element being disposed between the one of the second wiring lines and the first transistor, between the first transistor and the first node, between the first node and the second transistor, or between the second transistor and the one of the fourth wiring lines, and the second non-volatile element being disposed at a location corresponding to a location of the first non-volatile element, between the one of the third wiring lines and the third transistor, between the third transistor and the second node, between the second node and the fourth transistor, or between the fourth transistor and the one of the fifth wiring lines.
2. The memory according to claim 1 , wherein in each of the memory cells, the first non-volatile element is disposed between the one of the second wiring lines and the first transistor, and the second non-volatile element is disposed between the one of the third wiring lines and the third transistor.
3. The memory according to claim 1 , wherein in each of the memory cells, the first non-volatile element is disposed between the first transistor and the first node, and the second non-volatile element is disposed between the third transistor and the second node.
4. The memory according to claim 1 , wherein in each of the memory cells, the first non-volatile element is disposed between the first node and the second transistor, and the second non-volatile element is disposed between the second node and the fourth transistor.
5. The memory according to claim 1 , wherein in each of the memory cells, the first non-volatile element is disposed between the second transistor and the one of the fourth wiring lines, and the second non-volatile element is disposed between the fourth transistor and the one of the fifth wiring lines.
6. The memory according to claim 1 , wherein the fourth wiring lines and the fifth wiring lines being disposed along the first wiring lines.
7. The memory according to claim 1 , wherein the fourth wiring lines being disposed along the second wiring lines, and the fifth wiring lines being disposed along the third wiring lines.
8. A non-volatile memory comprising: a plurality of memory cells arranged in a matrix form; a plurality of first wiring lines each corresponding to memory cells of a common row; a plurality of second wiring lines and a plurality of third wiring lines, each of the plurality of second wiring lines corresponding to memory cells of a common column, each of the plurality of third wiring lines corresponding to memory cells of the common column; and a plurality of fourth wiring lines and fifth wiring lines, each of the plurality of fourth wiring lines and fifth wiring lines corresponding to the memory cells of one of the common row and the common column; each of the memory cells including a plurality of transistors, a first non-volatile element, a second non-volatile element, a first node, and a second node, the transistors including a first transistor, a second transistor, a third transistor, and a fourth transistor, the first transistor and the second transistor being connected in series, the third transistor and the fourth transistor being connected in series, the first node being disposed between the first transistor and the second transistor, the second node being disposed between the third transistor and the fourth transistor, gates of the first transistor and the third transistor being connected to one of the first wiring lines, a gate of the second transistor being connected to the second node, a gate of the fourth transistor being connected to the first node, the first transistor being connected between one of the second wiring lines and the first node, the second transistor being connected between the first node and one of the fourth wiring lines, the third transistor being connected between one of the third wiring lines and the second node, the fourth transistor being connected between the second node and the one of the fifth wiring lines, the first non-volatile element being connected between the first node and the gate of the fourth transistor, and the second non-volatile element being disposed between the second node and the gate of the second transistor.
9. The memory according to claim 8 , wherein the fourth wiring lines and the fifth wiring lines being disposed along the first wiring lines.
10. The memory according to claim 8 , wherein the fourth wiring lines being disposed along the second wiring lines, and the fifth wiring lines being disposed along the third wiring lines.
11. A non-volatile memory comprising: a plurality of memory cells arranged in a matrix form; a plurality of first global wiring lines each corresponding to memory cells of a common row; a plurality of second global wiring lines and a plurality of third global wiring lines; a plurality of fourth global wiring lines each corresponding to the memory cells of a common column; and a plurality of fifth global wiring lines and a plurality of sixth global wiring lines, each of the memory cells including a plurality of memory units, a selection circuit, a first local wiring line, a second local wiring line, and a third local wiring line, the second global wiring lines and the third global wiring lines corresponding to the memory units of the memory cells of the common column, in each of the memory cells, each of the memory units including a plurality of transistors, a first non-volatile element, a second non-volatile element, a first node, and a second node, the transistors including a first transistor, a second transistor, a third transistor, and a fourth transistor, the first transistor and the second transistor being connected in series with the first non-volatile element, the third transistor and the fourth transistor being connected in series with the second non-volatile element, the first node being disposed between the first transistor and the second transistor, the second node being disposed between the third transistor and the fourth transistor, gates of the first transistor and the third transistor being connected to the first local wiring line, a gate of the second transistor being connected to the second node, a gate of the fourth transistor being connected to the first node, the first transistor being connected between a corresponding second global wiring line and the first node, the second transistor being connected between the first node and the second local wiring line, the third transistor being connected between a corresponding third global wiring line and the second node, the fourth transistor being connected between the second node and the third local wiring line, the first non-volatile element being disposed between the corresponding second global wiring line and the first transistor, between the first transistor and the first node, between the first node and the second transistor, or between the second transistor and the second local wiring line, the second non-volatile element being disposed between the corresponding third global wiring line and the third transistor, between the third transistor and the second node, between the second node and the fourth transistor, or between the fourth transistor and the third local wiring line, at a location corresponding to a location of the first non-volatile element, and the selection circuit selecting the first local wiring line, the second local wiring line, the third local wiring line based on a signal from a corresponding first global wiring line, a signal from a corresponding fourth global wiring line, a signal from a corresponding fifth global wiring line, and a signal from a corresponding sixth global wiring line.
12. The non-volatile memory according to claim 11 , wherein the selection circuit includes a first selection unit, a second selection unit, and a third selection unit, the first selection unit selects the first local wiring line based on the signal from the corresponding first global wiring line and the signal from the corresponding fourth global wiring line, the second selection unit selects the second local wiring line based on the signal from the corresponding fourth global wiring line and the signal from the corresponding fifth global wiring line, the third selection unit selects the third local wiring line based on the signal from the corresponding fourth global wiring line and the signal from the corresponding sixth global wiring line, each of the fifth global wiring lines corresponds to the memory cells of the common row, and each of the sixth global wiring lines corresponds to the memory cells of the common row.
13. The non-volatile memory according to claim 11 , wherein the selection circuit includes a first selection unit, a second selection unit, and a third selection unit, the first selection unit selects the first local wiring line based on the signal from the corresponding first global wiring line and the signal from the corresponding fourth global wiring line, the second selection unit selects the second local wiring line based on a signal from a first selection unit and the signal from the corresponding fifth global wiring line, and the third selection unit selects the third local wiring line based on the signal from the first selection unit and the signal from the corresponding sixth global wiring line, each of the fifth global wiring lines corresponds to the memory cells of the common column, and each of the sixth global wiring lines corresponds to the memory cells of the common column.
14. A non-volatile memory comprising: a plurality of memory cells arranged in a matrix form; a plurality of first global wiring lines each corresponding to memory cells of a common row; a plurality of second global wiring lines and a plurality of third global wiring lines; a plurality of fourth global wiring lines each corresponding to memory cells of a common column; and a plurality of fifth global wiring lines, each of the memory cells including a plurality of memory units, a selection circuit, a first local wiring line, and a second local wiring line, the second global wiring lines and the third global wiring lines corresponding to the memory units of the memory cells of the common column, in each of the memory cells, each of the memory units including a plurality of transistors, a first non-volatile element, a second non-volatile element, a first node, and a second node, the transistors including a first transistor, a second transistor, a third transistor, and a fourth transistor, the first transistor and the second transistor being connected in series with the first non-volatile element, the third transistor and the fourth transistor being connected in series with the second non-volatile element, the first node being disposed between the first transistor and the second transistor, the second node being disposed between the third transistor and the fourth transistor, gates of the first transistor and the third transistor being connected to the first local wiring line, a gate of the second transistor being connected to the second node, a gate of the fourth transistor being connected to the first node, the first transistor being connected between a corresponding second global wiring line and the first node, the second transistor being connected between the first node and the second local wiring line, the third transistor being connected between a corresponding third global wiring line and the second node, the fourth transistor being connected between the second node and the second local wiring line, the first non-volatile element being disposed between the corresponding second global wiring line and the first transistor, between the first transistor and the first node, between the first node and the second transistor, or between the second transistor and the second local wiring line, the second non-volatile element being disposed between the corresponding third global wiring line and the third transistor, between the third transistor and the second node, between the second node and the fourth transistor, or between the fourth transistor and the second local wiring line, at a location corresponding to a location of the first non-volatile element, and the selection circuit selecting the first local wiring line and the second local wiring line based on a signal from a corresponding first global wiring line, a signal from a corresponding fourth global wiring line, and a signal from a corresponding fifth global wiring line.
15. The non-volatile memory according to claim 14 , wherein the selection circuit includes a first selection unit and a second selection unit, the first selection unit selects the first local wiring line based on the signal from the corresponding first global wiring line and the signal from the corresponding fourth global wiring line, the second selection unit selects the second local wiring line based on the signal from the corresponding fourth global wiring line and the signal from the corresponding fifth global wiring line, and each of the fifth global wiring lines corresponds to the memory cells of the common row.
16. The non-volatile memory according to claim 14 , wherein the selection circuit includes a first selection unit and a second selection unit, the first selection unit selecting the first local wiring line based on the signal from the corresponding first global wiring line and the signal from the corresponding fourth global wiring line, the second selection unit selecting the second local wiring line based on a signal from the first selection unit and the signal from the corresponding fifth global wiring line, and each of the fifth global wiring lines corresponds to the memory cells of the common column.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 18, 2014
August 18, 2015
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.