Discrete three-dimensional vertical memory

1. A discrete three-dimensional vertical memory (3D-M V ), comprising: a 3D-array die comprising a substrate and at least a 3D-M V array including a plurality of vertical memory strings, each of said vertical memory strings comprising a plurality of vertically stacked memory cells; a voltage-generator die comprising at least a portion of a voltage generator for providing said 3D-array die with at least a voltage other than the voltage supply, wherein said portion of said voltage generator is absent from said 3D-array die; wherein said 3D-array die comprises more back-end-of-line (BEOL) layers than said voltage-generator die; and, said 3D-array die and said voltage-generator die are separate dice.

2. The memory according to claim 1 , wherein each of said vertical memory strings includes a portion of said substrate.

3. The memory according to claim 1 , wherein each of said vertical memory strings is in contact with said substrate.

4. The memory according to claim 1 , wherein each of said vertically stacked memory cells comprises a vertical transistor.

5. The memory according to claim 1 , wherein said vertical transistor comprises a vertical channel.

6. The memory according to claim 1 , wherein each of said vertically stacked memory cells is a vertical-NAND cell.

7. The memory according to claim 1 , wherein said 3D-M V array does not comprise any under-array peripheral circuit.

8. The memory according to claim 1 , wherein said voltage-generator die comprises horizontal transistors.

9. The memory according to claim 1 , wherein said voltage generator comprises a read-voltage generator.

10. The memory according to claim 1 , wherein said voltage generator comprises a write-voltage generator.

11. The memory according to claim 1 , wherein said voltage generator comprises a band-gap reference generator.

12. The memory according to claim 1 , wherein said voltage generator comprises V R generator.

13. The memory according to claim 1 , wherein said voltage generator comprises a charge-pump circuit, a boost converter, a low-dropout regulator, or a buck converter.

14. The memory according to claim 1 , wherein said 3D-array die and said voltage-generator die are located in a memory package, a memory module, a memory card, or a solid-state drive.

15. The memory according to claim 1 , further comprising: another 3D-array die comprising another substrate and at least another 3D-M V array including another plurality of vertical memory strings; wherein said voltage-generator die comprises at least another portion of another voltage generator for said another 3D-array die.

16. The memory according to claim 15 , wherein each vertical memory string in said another 3D-array die includes another portion of said another substrate.

17. The memory according to claim 15 , wherein said another 3D-M V array does not comprise any under-array peripheral circuit.

18. The memory according to claim 15 , wherein said 3D-array die, said another 3D-array die and said voltage-generator die are located in a memory package, a memory module, a memory card, or a solid-state drive.

19. The memory according to claim 1 , wherein said 3D-M V is a three-dimensional read-only memory (3D-ROM) or a three-dimensional random-access memory (3D-RAM).

20. The memory according to claim 1 , wherein said 3D-M V is a 3D-memristor, 3D-RRAM or 3D-ReRAM, a 3D-PCM, a 3D-PMC, or a 3D-CBRAM.