Selective local metal cap layer formation for improved electromigration behavior

1. A method of forming a wiring structure for an integrated circuit device, the method comprising: forming a first metal line within an interlevel dielectric (ILD) layer, and forming a second metal line in the ILD layer adjacent the first metal line; forming a sacrificial hardmask layer over the ILD layer and first and second metal lines; patterning and removing portions of the sacrificial hardmask layer, thereby masking selected regions of the first and second metal lines such that first portions of the first and second copper lines are covered and second portions of the first and second copper lines are not covered so as to define exposed regions; selectively plating metal cap regions over only the exposed regions of the first and second metal lines at periodic intervals such that the metal cap regions are not initially plated over the covered portions of the one or more copper lines, and such that a spacing between adjacent metal cap regions of an individual metal line corresponds to a critical length, L, at which a back stress gradient balances an electromigration force in the individual metal line, so as to suppress mass transport of electrons; wherein the metal cap regions of the first metal line are formed at staggered locations with respect to the metal cap regions of the second metal line, along a common longitudinal axis; and following the plating of the metal cap regions over the exposed regions of the first and second metal lines, removing remaining portions of the sacrificial hardmask layer and forming a conformal insulator layer over the metal cap regions, uncapped regions of the first and second metal lines, and the ILD layer.

2. The method of claim 1 , wherein a dimension, S, represents a lateral spacing between closest metal cap regions from the first and second metal lines, and wherein the metal cap regions of the first and second metal lines are arranged so that S is maximized in order to reduce the electric field between closest pairs of metal cap regions of the first and second metal lines.

3. The method of claim 2 , wherein S is selected to be maximized such that the metal cap regions of the first metal line are shifted by about one-half period relative to the metal cap regions of the second metal line.

4. The method of claim 3 , wherein the metal cap regions comprise one or more of: tantalum, (Ta), tantalum nitride (TaN), cobalt (Co), cobalt tungsten phosphide (CoWP), and ruthenium (Ru).

5. The method of claim 1 , wherein patterning and removing portions of the sacrificial hardmask layer further comprises etching into a top surface of the first and second metal lines such that at least a portion of the metal cap regions is disposed below the top surface of the first and second metal lines.

6. A method of forming a wiring structure for an integrated circuit device, the method comprising: forming a first metal line within an interlevel dielectric (ILD) layer, and forming a second metal line in the ILD layer adjacent the first metal line; masking selected regions of the first and second metal lines; selectively plating metal cap regions over exposed regions of the first and second metal lines at periodic intervals such that a spacing between adjacent metal cap regions of an individual metal line corresponds to a critical length, L, at which a back stress gradient balances an electromigration force in the individual metal line, so as to suppress mass transport of electrons; and wherein the metal cap regions of the first metal line are formed at staggered locations with respect to the metal cap regions of the second metal line, along a common longitudinal axis; forming a sacrificial hardmask layer over the ILD layer and first and second metal lines; wherein the sacrificial hardmask layer comprises: a hydrogen doped silicon nitride layer formed on the ILD layer and first and second metal lines; a titanium nitride layer formed on the hydrogen doped silicon nitride layer; a low temperature oxide (LTO) layer formed on the titanium nitride layer; and an organic planarizing layer (OPL) formed over the LTO layer; patterning and removing portions of the sacrificial hardmask layer, wherein patterning and removing portions of the sacrificial hardmask layer further comprises etching into a top surface of the first and second metal lines such that at least a portion of the metal cap regions is disposed below the top surface of the first and second metal lines; and following the plating of the metal cap regions over the exposed regions of the first and second metal lines, removing remaining portions of the sacrificial hardmask layer and forming a conformal insulator layer over the metal cap regions, uncapped regions of the first and second metal lines, and the ILD layer.

7. The method of claim 6 , wherein patterning and removing portions of the sacrificial hardmask layer further comprises: defining a pattern in the OPL and the LTO layer; transferring the pattern through the titanium nitride layer and partially into the hydrogen doped silicon nitride layer; removing the OPL and the LTO layer by ashing; removing the titanium nitride layer by etching; transferring the pattern completely through the hydrogen doped silicon nitride layer; and following the plating of the metal cap regions, removing remaining portions of the hydrogen doped silicon nitride layer.