Disclosed herein are thin film transistors (TFTs) and techniques for fabricating TFTs. A major plane of the gate electrode of the TFT may be vertically oriented with respect to a horizontal layer of polysilicon in which the TFT resides. An interface between the gate electrode and gate dielectric may be vertically oriented with respect to a horizontal layer of polysilicon in which the TFT resides. The TFT may have a channel width that is defined by a thickness of the horizontal layer of polysilicon. The TFT may be formed by etching a hole in a layer of polysilicon. Then, a gate electrode and gate dielectric may be formed in the hole by depositing layers of dielectric and conductor material on the sidewall. The body may be formed in the horizontal layer of polysilicon outside the hole.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A device comprising: a semiconductor substrate that has a major surface that extends in a horizontal plane; and a horizontal layer comprising conductor material above the semiconductor substrate, wherein the horizontal layer has a major surface that extends in the horizontal plane; a thin film transistor (TFT) in the horizontal layer, the TFT including: a gate electrode; a gate dielectric surrounding the gate electrode, an interface between the gate electrode and gate dielectric extending vertically with respect to the horizontal plane, wherein the conductor material of the horizontal layer surrounds the gate dielectric; a body, a source, and a drain that reside in the conductor material of the horizontal layer; wherein the body is adjacent to the gate dielectric, an interface between the gate dielectric and the body extending vertically with respect to the horizontal plane, the body having a first end and a second end; wherein the source is at the first end of the body, wherein the source is in direct electrical contact with a first region of the conductor material in the horizontal layer; and wherein the drain is at the second end of the body, wherein the drain is in direct electrical contact with a second region of the conductor material in the horizontal layer, wherein the body comprises a channel that extends from the source to the drain.
2. The device of claim 1 , wherein the thin film transistor comprises: two gate electrodes back to back; two gate dielectrics; and two bodies.
3. The device of claim 2 , wherein the two bodies include a first body having a first channel and a second body having a second channel, the first and second channels run parallel to each other.
4. The device of claim 2 , further comprising an insulator between the two gates.
5. The device of claim 1 , wherein the gate electrode is entirely within the horizontal layer and the body is entirely within the horizontal layer.
6. The device of claim 1 , wherein the horizontal layer is a first of a plurality of horizontal layers comprising conductor material comprising polysilicon, wherein the device further comprises a plurality of horizontal insulator layers alternating with the plurality of horizontal layers in a stack.
7. The device of claim 1 , further comprising: a body extension that extends the body away from the gate electrode.
8. A 3D stacked non-volatile memory device comprising: a semiconductor substrate that has a major surface that extends in a horizontal plane; a plurality of horizontal layers comprising conductor material above the substrate, wherein the conductor material in the respective horizontal layers has a major surface that extends in the horizontal plane, each of the plurality of horizontal layers having a memory array region and a word line select gate region; a plurality of horizontal insulator layers alternating with the plurality of horizontal layers comprising the conductor material in a stack above the semiconductor substrate; a plurality of memory cells in the memory array region of each of the horizontal layers comprising conductor material, wherein respective portions of the conductive material serve as a control gate for respective ones of the memory cells; and a set of thin film transistors (TFTs) in the word line select gate regions of different ones of the horizontal layers comprising conductor material, ones of the TFTs in the set including: a gate electrode; a gate dielectric adjacent to the gate electrode, an interface between the gate electrode and gate dielectric extending vertically with respect to the horizontal layer comprising conductor material; and a body adjacent to the gate dielectric, an interface between the gate dielectric and body extending vertically with respect to the horizontal layer comprising conductor material in which the TFT resides, the body having a first end and a second end; a first source/drain at the first end of the body, wherein the first source/drain is electrically connected to a first portion of the conductor material that is in the memory array region in the horizontal layer in which the TFT resides, wherein the first portion is in direct electrical contact with the control gates of a group of memory cells; and a second source/drain at the second end of the body, wherein the second source/drain is electrically connected to a second portion of the conductor material that is in the word line select gate region in the horizontal layer in which the TFT resides, wherein the body comprises a channel that extends from the first source/drain to the second source/drain.
9. The 3D stacked non-volatile memory device of claim 8 , wherein the ones of the TFTs comprise: two gate electrodes back to back; two gate dielectrics; and two bodies.
10. The 3D stacked non-volatile memory device of claim 9 , wherein the two bodies include a first body having a first channel and a second body having a second channel, the first and second channels run parallel to each other.
11. The 3D stacked non-volatile memory device of claim 9 , further comprising an insulator between the two gates.
12. The 3D stacked non-volatile memory device of claim 9 , wherein the ones of the TFTs comprise: a body extension that extends the body away from the gate electrode towards the memory array region.
13. The device of claim 1 , wherein the body has a channel width that is defined by a thickness of the horizontal layer.
14. The device of claim 1 , further comprising a circuit that is configured to apply a signal to the gate electrode to cause the TFT to electrically connect the first region of the conductor material to the second region of the conductor material.
15. The device of claim 1 , further comprising: a driver circuit that is electrically coupled to the first region of the conductor material of the horizontal layer comprising conductor material; and a plurality of memory cells each having a control gate, wherein the second region of the conductor material is electrically coupled to the control gates of the plurality of memory cells.
16. A 3D stacked non-volatile memory device comprising: a semiconductor substrate that has a major surface that extends in a horizontal plane; a plurality of horizontal layers comprising conductor material above the substrate, wherein the conductor material in the respective horizontal layers has a major surface that extends in the horizontal plane; a plurality of memory cells each having a control gate, wherein respective portions of the conductive material serve as the control gate for respective ones of the memory cells; and a set of thin film transistors (TFTs), wherein each of the TFTs resides in one of the plurality of horizontal layers, ones of the TFTs in the set including: a gate electrode; a gate dielectric adjacent to the gate electrode, an interface between the gate electrode and gate dielectric extending in a vertical direction with respect to the horizontal plane; and a body adjacent to the gate dielectric, an interface between the gate dielectric and body extending the vertical direction, the body having a first end and a second end; a first source/drain at the first end of the body, wherein a first portion of the conductor material of a first of the plurality of horizontal layers electrically connects the control gates of a set of the plurality of memory cells to the first source/drain; and a second source/drain at the second end of the body, wherein the body comprises a channel that extends from the first source/drain to the second source/drain; and management circuitry that applies a first signal to the second source/drain of a given TFT of the set of TFTs while the management circuitry applies a second signal to the gate electrode of the given TFT to pass the first signal to the control gates of the set of memory cells associated with the given TFT.
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January 2, 2013
September 8, 2015
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