A method of forming a semiconductor device includes forming a first transistor and a second transistor on a substrate, monitoring processes of forming the first and second transistors to find an error and performing an additional ion implantation process to form a low-concentration dopant region or a halo region on the first transistor or the second transistor corresponding to a found error.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of forming a semiconductor device, comprising: forming a first transistor and a second transistor on a substrate, wherein forming the first transistor and the second transistor comprises: forming a device isolation layer on or in the substrate to define a first active region corresponding to a first column and a second active region corresponding to a second column; performing a channel ion implantation process on the first and second active regions; forming a first gate pattern and a second gate pattern on the first active region and the second active region, respectively; performing a low-concentration dopant ion implantation process to form a first low-concentration dopant region in the substrate at first and second sides of the first gate pattern and a second low-concentration dopant region in the substrate at first and second sides of the second gate pattern; and performing a halo ion implantation process to form a first halo region and a second halo region contacting the first low-concentration dopant region and the second low-concentration dopant region under the first gate pattern and the second gate pattern respectively; monitoring processes of forming the first and second transistors to find an error, wherein the error is found by determining a mask misalignment in the low-concentration dopant ion implantation process or the halo ion implantation process; using back data to determine a variation degree of a threshold voltage corresponding to the mask misalignment, wherein the back data includes a plurality of threshold voltage variation degrees corresponding to different misalignment degrees; and performing an additional ion implantation process to adjust a threshold voltage of the low-concentration dopant region or the halo region on the first transistor or the second transistor corresponding to the determined variation degree.
2. The method of claim 1 , wherein monitoring the processes of forming the first and second transistors comprises: performing an overlay test to find the mask misalignment.
3. The method of claim 1 , further comprising, before forming the first and second transistors: forming preliminary transistors under various mask misalignment conditions; and measuring threshold voltages of the preliminary transistors to gather the back data.
4. The method of claim 1 , wherein if a threshold voltage of the first transistor is smaller than a threshold voltage of the second transistor, the additional ion implantation process for the formation of the halo region is performed using an ion implantation mask which exposes the first active region and covers the second active region.
5. The method of claim 1 , wherein if a threshold voltage of the first transistor is greater than a threshold voltage of the second transistor, the additional ion implantation process for the formation of the low-concentration dopant region is performed using an ion implantation mask which exposes the first active region and covers the second active region.
6. The method of claim 1 , wherein if a threshold voltage of the second transistor is smaller than a threshold voltage of the first transistor, the additional ion implantation process for the formation of the halo region is performed using an ion implantation mask which exposes the second active region and covers the first active region.
7. The method of claim 1 , wherein if a threshold voltage of the second transistor is greater than a threshold voltage of the first transistor, the additional ion implantation process for the formation of the low-concentration dopant region is performed using an ion implantation mask which exposes the second active region and covers the first active region.
8. The method of claim 1 , further comprising, after performing the additional ion implantation process: forming a first spacer and a second spacer on sidewalls of the first and second gate patterns, respectively; and forming a first high-concentration dopant region and a second high-concentration dopant region in the substrate adjacent to sidewalls of the first and second spacers, respectively.
9. The method of claim 1 , wherein the additional ion implantation process changes a threshold voltage of the first or second transistor.
10. A method of monitoring a semiconductor device comprising: receiving an error signal indicating an error has occurred when forming a first transistor on a substrate, wherein the error is found by determining a mask misalignment in a first ion implantation process, and wherein the first ion implantation process is monitored for errors while it is being performed; using back data to determine a variation degree of a threshold voltage corresponding to the mask misalignment, wherein the back data includes a plurality of threshold voltage variation degrees corresponding to different misalignment degrees; and outputting, based on the error, a command instructing a process used in the forming of the first transistor to be repeated, wherein the process includes a second ion implantation process and wherein the second ion implantation process adjusts a threshold voltage of the first transistor according to the determined variation degree.
11. The method of claim 10 , wherein the command includes a mask type to he used in the repeated process.
12. The method of claim 11 , Wherein the mask type is based on a threshold voltage difference between the first transistor and a second transistor.
13. A method of forming a semiconductor device, comprising: performing a first ion implantation process on a first transistor and a second transistor; and performing, in response to an error indication, a second ion implantation process on the first transistor, wherein the second ion implantation process adjusts a threshold voltage of the first transistor and uses a different mask than a mask used in the first ion implantation process, wherein the error indication is generated by determining a mask misalignment in the first ion implantation process, wherein back data is used to determine a variation degree of the threshold voltage which corresponds to the mask misalignment, and wherein the back data includes a plurality of threshold voltage variation degrees corresponding to different misalignment degrees.
14. The method of claim 13 , wherein the second ion implantation process includes a halo ion implantation process or a lightly doped drain ion implantation process.
15. The method of claim 14 , wherein the first and second ion implantation processes are the same type.
16. The method of claim 13 , further comprising forming a spacer on sidewalls of each of the first and second transistors.
17. The method of claim 13 , wherein the threshold voltage of the first transistor and a threshold voltage of the second transistor are the same after the second ion implantation process.
18. The method of claim 13 , wherein the semiconductor device is a static random access memory.
19. The method of claim 13 , wherein a low-concentration dopant region of the first transistor is formed to have a different type of dopant, a different dopant concentration, or a different region shape from that of a low-concentration dopant region of the second transistor after the second ion implantation process.
20. The method of claim 13 , wherein a halo region of the first transistor is formed to have a different type of dopant, a different dopant concentration, or a different region shape from that of a halo region of the second transistor after the second ion implantation process.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 12, 2013
September 15, 2015
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