The present invention relates to a sensor-integrated chip for a CCD camera in which a CCD sensor, an H/V driver for driving the CCD sensor, and an ISP (Image Signal Process) chip, which inputs a control signal for driving the CCD sensor to the H/V driver and allows a video to be displayed on a monitor (not shown) in response to an output signal from the CCD sensor, are stacked and connected with each other by inter-pad wire bonding into one IC package to be one chip, by an SIP (system In Package) method.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A sensor-integrated chip for a CCD camera, comprising: a charged coupled device (CCD) sensor chip sensing incident light and including a charged coupled device (CCD) sensor; a signal driving chip that drives the CCD sensor chip; an image signal processing (ISP) chip integrated with peripheral circuits for image processing, wherein the ISP chip includes at least one or more of an analog front end (AFE) that converts an analog signal from the CCD sensor into a digital signal, an image signal processing that processes a digitalized video, and a timing generator (TG) that generates a signal for driving the CCD sensor in response to control of the image signal processing; wherein the ISP chip, the signal driving chip and the CCD sensor chip are stacked in the described order and connected by inter-pad wire bonding into one package to be a single chip, a board on which the single chip is disposed, wherein the single chip and the board are connected by wire bonding for a package; and a heat-dissipating pad having a bore formed in a center thereof, wherein the single chip and the board is placed in the bore not to contact with the heat-dissipating pad and in order not to block an upper front portion of the CCD sensor chip, and wherein the signal driving chip, the ISP chip, and the board are connected to the heat-dissipating pad through wires for transferring heat generated by the signal driving chip and the ISP chip.
2. The sensor-integrated chip according to claim 1 , wherein a protective layer for reducing noise due to signal interference and blocking heat generated by a high-voltage circuit is formed under each of the CCD sensor chip, the signal driving chip and the ISP chip.
3. The sensor-integrated chip according to claim 1 , further comprising a housing surrounding and supporting the CCD sensor chip, the signal driving chip, and the ISP chip.
4. The sensor-integrated chip according to claim 1 , wherein a color filter array and a microlens are disposed at an upper front portion of the CCD sensor chip.
5. The sensor-integrated chip according to claim 1 , wherein the signal driving chip includes an H/V (Horizontal/Vertical) driver, an H-driver, or a V-driver.
6. The sensor-integrated chip according to claim 1 , wherein the ISP chip further comprises a power management that supplies a driving voltage and blocks overvoltage/overcurrent.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 21, 2012
September 22, 2015
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