Semiconductor system and method of operating the same

1. A semiconductor system, comprising: a data storage unit including memory blocks, a circuit group and a control circuit, wherein the memory blocks store data therein and are arranged in a longitudinal direction and a vertical direction, the circuit group is suitable for performing a program, read or erase operation on the memory blocks, and the control circuit controls the circuit group; and a memory control unit suitable for controlling the data storage unit, wherein each of the memory blocks include a plurality of sub-memory blocks, wherein the sub-memory blocks arranged in the longitudinal direction share bit lines and do not share word lines and source lines, and the sub-memory blocks arranged in the vertical direction share the bit lines or the source lines.

2. The semiconductor system of claim 1 , wherein word lines of some of the sub-memory blocks arranged in the vertical direction, are coupled in common to a first word line group, and word lines of other sub-memory blocks are coupled in common to a second word line group.

3. The semiconductor system of claim 2 , wherein the sub-memory blocks coupled to the first word line group and the sub-memory blocks coupled to the second word line group are stacked in vertical columns or in zigzag patterns.

4. The semiconductor system of claim 1 , wherein the circuit group comprises: a voltage generator suitable for generating voltages including various levels in response to an operation signal; a row decoder suitable for transferring the voltages generated by the voltage generator to a selected memory block in response to a row address; a column decoder suitable for exchanging data with the selected memory block in response to a column address; and an input/output circuit suitable for transferring data, input from exterior, to the column decoder or data, input from the column decoder, to the control circuit or the exterior.

5. A method of operating a semiconductor system, the method comprising: during an erase operation of the semiconductor system including memory blocks arranged in a longitudinal direction and a vertical direction and including first sub-memory blocks and second sub-memory blocks, increasing a voltage difference between a channel and memory cells of the first sub-memory block of a selected memory block to erase the memory cells included in the first sub-memory block of the selected memory block; and reducing a voltage difference between a channel and memory cells of the second sub-memory block of the selected memory block when the memory cells of the first sub-memory block are erased to not erase the memory cells included in the second sub-memory block of the selected memory.

6. The method of claim 5 , wherein to erase the memory cells included in the first sub-memory block of the selected memory block, a first erase voltage is applied to a source line group coupled to the first sub-memory block of the selected memory block, a first turn-on voltage is applied to a source selection line, a first word line voltage is applied to word lines, and a second turn-on voltage lower than the first turn-on voltage is applied to a drain selection line, and a second erase voltage lower than the first erase voltage is applied to bit lines.

7. The method of claim 6 , wherein the second erase voltage is applied to a source line group coupled to the second sub-memory block of the selected memory block, the second turn-on voltage is applied to a source selection line, a second or third word line voltage higher than the first word line voltage is applied to word lines, the second turn-on voltage is applied to a drain selection line, and the second erase voltage is applied to bit lines to not erase the memory cells included in the second sub-memory block of the selected memory block when the memory cells of the first sub-memory block are erased.

8. The method of claim 6 , wherein when the first sub-memory blocks and the second sub-memory blocks of different memory blocks, stacked in the vertical direction, are stacked in zigzag patterns, the first turn-on voltage is applied to a source selection line coupled to the second sub-memory block of a neighboring memory block sharing the source line group of the first sub-memory block included in the selected memory block, a second or third word line voltage is applied to word lines, the second turn-on voltage is applied to a drain selection line, and the second erase voltage is applied to bit lines to not erase memory cells included in the second sub-memory block of the neighboring memory block.

9. The method of claim 8 , wherein to not erase memory cells included in the first sub-memory blocks of remaining memory blocks, except the selected memory block, among the selected memory block and the memory blocks stacked in the vertical direction, the second erase voltage is applied to bit lines and source line groups coupled to the first sub-memory blocks of the remaining memory blocks, a second turn-on voltage is applied to source selection lines, the second or the third word line voltage is applied to word lines, and the second turn-on voltage is applied to a drain selection line.

10. The method of claim 8 , wherein to not erase memory cells included in the second sub-memory blocks of remaining memory blocks, except the second sub-memory block of the selected memory block and the neighboring memory block, among the selected memory block and the memory blocks stacked in the vertical direction, the second erase voltage is applied to source line groups and bit lines coupled to the second sub-memory blocks of the remaining memory blocks, the second turn-on voltage is applied to source selection lines, the second or third word line voltage is applied to word lines, and the second turn-on voltage is applied to a drain selection line.

11. The method of claim 6 , wherein to not erase memory cells included in the first sub-memory block of a neighboring memory block sharing the source line group of the first sub-memory block included in the selected memory block when the first sub-memory blocks of different memory blocks stacked in the vertical direction are stacked on each other, and the second sub-memory blocks of the different memory blocks, stacked in the vertical direction, are stacked on each other, the second turn-on voltage is applied to a source selection line coupled to the first sub-memory block of the neighboring memory block, the first word line voltage is applied to word lines, the second turn-on voltage is applied to a drain selection line, and the second erase voltage is applied to bit lines.

12. The method of claim 11 , wherein to not remove memory cells included in the first and second sub-memory blocks of remaining memory blocks, except the first sub-memory blocks of the selected memory block and the neighboring memory block, the second erase voltage is applied to bit lines and source line groups coupled to the first and second sub-memory blocks of the remaining memory blocks, the second turn-on voltage is applied to source selection lines, the first word line voltage is applied to word lines, and the second turn-on voltage is applied to a drain selection line.

13. The method of claim 11 , wherein the first turn-on voltage is applied to source selection lines coupled to the first sub-memory block of the neighboring memory block, the first word line voltage is applied to word lines, the second turn-on voltage is applied to drain selection lines, and the second erase voltage is applied to bit lines to erase the memory cells included in the first sub-memory block of the neighboring memory block when the neighboring memory block sharing the source line group of the first sub-memory block, included in the selected memory block, is further selected during the erase operation.

14. The method of claim 11 , wherein when another memory block, not sharing the source line group and the bit lines with the first sub-memory block included in the selected memory block, among the selected memory block and the memory blocks stacked in the vertical direction, is further selected during the erase operation, the first turn-on voltage is applied to source selection lines coupled to the first sub-memory block of another memory block, the first word line voltage is applied to word lines, the second turn-on voltage is applied to drain selection lines, and the second erase voltage is applied to bit lines in order to erase memory cells included in the first sub-memory block of another memory block.

15. The method of claim 6 , wherein the first erase voltage is 18V, the second erase voltage is 9V, the first turn-on voltage is 15V, the second turn-on voltage is 7V, and the first word line voltage is 0V.

16. The method of claim 7 , wherein the second word line voltage is 9V, and the third word line voltage is 18V.

17. A semiconductor system, comprising: a plurality of memory blocks configured to store data and be arranged in a longitudinal direction and a vertical direction, wherein each of the plurality of memory blocks include a plurality of sub-memory blocks in which the plurality of sub-memory blocks configured in the longitudinal direction share bit lines and do not share word lines and source lines and the plurality of sub-memory blocks configured in the vertical direction share bit lines or source lines; and a memory control unit configured to control the plurality of memory blocks.

18. The semiconductor system of claim 17 , wherein different voltages are applied to a first source line group and a second source line group.

19. The semiconductor system of claim 17 , wherein different voltages are applied to a first word line group and a second word line group.

20. The semiconductor system of claim 17 , wherein during an erase operation, different voltages are applied are applied to a first word line group and a second line group in which the first word line group is electrically coupled to first sub-memory blocks and the second word line group is electrically coupled to second sub-memory blocks.