A gate insulating film of a conventional semiconductor device is subjected to dielectric breakdown at a low electric field strength and thus its service life is short. This is because since the size of the asperity of at least one of a semiconductor layer-side interface and an electrode-side interface is large and, an electric field applied to the gate insulating film is locally concentrated and has a variation in its strength. This problem is solved by specifying the sizes of the asperities of both interfaces of the gate insulating film.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: a semiconductor layer; a gate insulating film in contact with the semiconductor layer with an interface formed therebetween; and a gate electrode layer in contact with the insulating film with an interface formed therebetween on a side opposite to the semiconductor layer, wherein asperity of the interface between the semiconductor layer and the gate insulating film and asperity of the interface between the gate insulating film and the gate electrode layer each have a size which decreases correspondingly as a thickness of the gate insulating film decreases in a region of a length of 1 μm in a direction parallel to a direction in which the gate insulating film extends; wherein the size of the asperity of the interface between the semiconductor layer and the gate insulating film is 10% or less of the thickness of the gate insulating film and the size of the asperity of the interface between the gate insulating film and the gate electrode layer is 10% or less of the thickness of the gate insulating film.
2. The semiconductor device according to claim 1 , wherein the asperities of both interfaces are each a minimum step between atoms in a plane orientation of the semiconductor layer.
3. A method of manufacturing a semiconductor device comprising: a semiconductor layer; a gate insulating film in direct contact with the semiconductor layer; and a gate electrode in direct contact with the gate insulating film on a side opposite to the semiconductor layer, the method comprising as its steps: a flattening step of causing a size of asperity of a surface of the prepared semiconductor layer to be 10% or less of a thickness of the gate insulating film to be formed; and a gate insulating film forming step of forming the gate insulating film by oxidation, oxynitriding, or nitriding method which renders a size of asperity of an interface between the semiconductor layer and the gate insulating film contacted with each other into 10% or less of the thickness of the gate insulating film and which renders a size of asperity of a surface of the gate insulating film and the electrode into 10% or less of the thickness of the gate insulating film to be formed.
4. The method of manufacturing a semiconductor device according to claim 3 , wherein the flattening step comprises a flattening step of rendering the asperity of the surface of the semiconductor layer to a minimum step between atoms in a plane orientation of the semiconductor layer, and wherein the gate insulating film forming step comprises a step of forming the gate insulating film by the oxidation, oxynitriding, or nitriding method so that the size of the asperity of the interface between the semiconductor layer and the gate insulating film contacted with each other and the size of the asperity of the surface of the gate insulating film to which the gate electrode is to be provided, each become equal to or substantially equal to a size of the step.
5. The method of manufacturing a semiconductor device according to claim 3 , wherein the flattening step comprises a step of forming an oxide film on the prepared semiconductor layer in an atmosphere of water or oxygen or in an atmosphere of a mixture of water and oxygen at a temperature of 900° C. or more and removing the formed oxide film using a chemical solution containing hydrofluoric acid.
6. The method of manufacturing a semiconductor device according to claim 3 , wherein the flattening step comprises a step of heat-treating the prepared semiconductor layer in an atmosphere of Ar, H 2 , or Ar/H 2 at a temperature of 800° C. or more after removing a natural oxide film of its surface.
7. A semiconductor device comprising: a semiconductor layer; a gate insulating film in direct contact with the semiconductor layer; and a gate electrode in direct contact with the gate insulating film on a side opposite to the semiconductor layer, wherein a thickness of the gate insulating film, asperity of an interface between the semiconductor layer and the gate insulating film, and asperity of an interface between the gate insulating film and the gate electrode are formed so that a size of the asperity of the interface between the semiconductor layer and the gate insulating film is reflected on a size of the asperity of the interface between the gate insulating film and the gate electrode; wherein the size of the asperity of the interface between the semiconductor layer and the gate insulating film is 10% or less of the thickness of the gate insulating film and the size of the asperity of the interface between the gate insulating film and the gate electrode layer is 10% or less of the thickness of the gate insulating film.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 16, 2012
October 6, 2015
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.