A semiconductor device includes: a channel region formed in a semiconductor substrate; a source region formed on one side of the channel region; a drain region formed on the other side of the channel region; a gate electrode formed on the channel region via a gate insulating film; and a stress-introducing layer that applies stress to the channel region, the semiconductor device having a stress distribution in which source region-side and drain region-side peaks are positioned between a pn junction boundary of the channel region and the source region and a pn junction boundary of the channel region and the drain region.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: a channel region in a semiconductor substrate; a source region at one end of the channel region; a drain region at another end of the channel region; a gate electrode over the channel region with a gate insulating film between the gate electrode and the channel region, the gate electrode including side walls having a curved shape; a stress-introducing layer configured to apply stress to the channel region, the stress-introducing layer having a portion disposed underneath the gate electrode; and a silicide layer extending partially along and partially embedded in a top surface of the source region or the drain region and including an end surface in direct contact with a lower portion of a first side-wall insulating film.
2. The semiconductor device according to claim 1 , further comprising: a source region-side peak and a drain region-side peak of a stress distribution positioned between a position of a source region-side peak and a position of a drain region-side peak of a carrier concentration distribution in the channel region.
3. The semiconductor device according to claim 1 , further comprising: a source region-side peak and a drain region-side peak of a stress distribution positioned underneath the gate electrode.
4. The semiconductor device according to claim 1 , further comprising: a source region-side peak of a stress distribution positioned in the channel region underneath one end portion of the gate electrode; and a drain region-side peak of the stress distribution is positioned in the channel region underneath the other end portion of the gate electrode.
5. The semiconductor device according to claim 1 , further comprising: a stress distribution peak in the channel region overlapping a potential distribution peak under applied operating voltage.
6. The semiconductor device according to claim 1 , further comprising: the first side-wall insulating film formed on the semiconductor substrate; and a depression formed in the first side-wall insulating film, wherein the gate electrode is formed in the depression via the gate insulating film.
7. The semiconductor device according to claim 6 , further comprising: another stress-introducing layer formed (i) over a region from the first side-wall insulating film on the side of the source region to the source region, and (ii) over a region from the first side-wall insulating film on the side of the drain region to the drain region.
8. The semiconductor device according to claim 1 , further comprising: another stress-introducing film covering a region above the channel region, the source region, and the drain region.
9. The semiconductor device according to claim 1 , wherein, the stress-introducing layer is formed in the semiconductor substrate on the both sides of the channel region, the source region is formed in at least a portion of the stress-introducing layer on one side of the channel region, and the drain region is formed in at least a portion of the stress-introducing layer on the other side of the channel region.
10. The semiconductor device according to claim 1 , wherein, the semiconductor substrate is formed of silicon, and the stress-introducing layer is formed of silicon germanium or silicon carbide.
11. The semiconductor device according to claim 1 , wherein the silicide layer extends only partially along the top surfaces of the source region and the drain region.
12. The semiconductor device according to claim 1 wherein the stress-introducing layer is formed of silicon germanium.
13. The semiconductor device according to claim 1 wherein the gate insulating film is formed of hafnium oxide dielectric material.
14. The semiconductor device according to claim 1 wherein the gate electrode is formed of a metal layer.
15. The semiconductor device according to claim 1 wherein the gate electrode is formed of a metal compound layer.
16. A semiconductor device comprising: a channel region in a semiconductor substrate; a gate electrode over the channel region with a gate insulating film between the gate electrode and the channel region; a source region and a drain region at ends of the channel region; a first stress-introducing layer in the semiconductor substrate and each side of the gate electrode; a silicide layer at surfaces of the source and drain regions; a second stress-introducing layer formed at each side of the gate electrode without contacting the gate electrode; a first side-wall insulating film between the second stress-introducing layer and the gate electrode; a second side-wall insulating film between the second stress-introducing layer and the first side-wall insulating film; and a third side-wall insulating film between the first side-wall insulating film and the gate electrode, the third side-wall insulating film having a first side positioned proximate to the first side-wall insulating film and a second side positioned proximate to the gate electrode, wherein, the second side of the third side-wall insulating film has a curved shape, and the gate electrode has a curved shape aligned with the second side of the third side-wall insulating film.
17. The semiconductor device of claim 16 , wherein the gate insulating film is between the gate electrode and the third side-wall insulating film, the gate insulating film having a curved shape aligned with the second side of the third side-wall insulating film.
18. The semiconductor device of claim 16 , wherein a width of a bottom portion of the gate electrode proximate to the semiconductor substrate is smaller than a width of an upper portion of the gate electrode.
19. The semiconductor device of claim 16 further comprising an extension region underneath the gate electrode.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 19, 2010
October 6, 2015
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.