A method of manufacturing a semiconductor package having a small gate clip is disclosed. A first and second semiconductor chips, each of which includes a source electrode and a gate electrode at a top surface, are attached on two adjacent lead frame units of a lead frame such that the lead frame unit with the first chip formed thereon is rotated 180 degrees in relation to the other lead frame unit with the second semiconductor chip formed thereon. A first and second clip sets are mounted on the first and second semiconductor chips, wherein the first clip set is connected to the gate electrode of the first chip, the source electrode of the second chip, and their corresponding leads and the second clip set is connected to the gate electrode of the second chip, the source electrode of the first chip and their corresponding leads.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of manufacturing a semiconductor package having a small gate clip structure comprising: providing a lead frame comprising a first lead frame unit and a second lead frame unit, each lead frame unit comprising a die pad and a first and second leads disposed at a side of the die pad and electrically isolated from the die pad; attaching a first semiconductor chip and a second semiconductor chip respectively on the die pad of each lead frame unit, each of the first semiconductor chip and the second semiconductor chip includes a first electrode and a second electrode at a top surface and a third electrode at a bottom surface opposite the top surface, wherein the first semiconductor chip and the second semiconductor chip are mounted on the die pad of the first and second lead frame unit with the third electrode electrically connected to the respective die pad; mounting a first clip set and a second clip set on the first and second semiconductor chips, wherein the first clip set is connected to the first electrode of the first semiconductor chip, the second electrode of the second semiconductor chip, and their corresponding leads on the lead frame and the second clip set is connected to the first electrode of the second semiconductor chip, the second electrode of the first semiconductor chip and their corresponding leads on the lead frame.
2. The method of claim 1 , wherein the first and second lead frame unit constituting as a rotational symmetry of order 2 image of each other.
3. The method of claim 2 , wherein each clip set comprising a first electrode contact area for contacting the first electrode and a second electrode contact area for contacting the second electrode, wherein an area of the first electrode is smaller than an area of the second electrode and the first electrode contact area being smaller than the area of the first electrode.
4. The method of claim 3 , wherein the second electrode contact area being substantially the same as the area of the second electrode.
5. The method of claim 3 , wherein each clip set further comprising a first lead contact area for contacting the first lead and a second lead contact area for contacting one or more second leads, wherein the second lead contact area is larger than the first lead contact area.
6. The method of claim 5 , wherein the first lead contact area is adjacent to the first electrode contact area and the second lead contact area is adjacent to the second electrode contact area.
7. The method of claim 6 , wherein the first lead contact area is adjacent to the second lead contact area.
8. The method of claim 6 , wherein each clip set further comprising a tie bar connection section between the first lead contact area and the second lead contact area.
9. The method of claim 8 , wherein the first electrode contact areas of the first and second sets of the clip are interconnected by a tie bar connection section there between.
10. The method of claim 1 , after mounting the first and second clip sets on the first and second semiconductor chips, further comprising forming a molding layer to encapsulate the first semiconductor chip, the second semiconductor chip, lead frame units, first clip set and the second clip set.
11. The method of claim 10 , after forming the molding layer, further comprising separating individual semiconductor packages by cutting between two adjacent lead frame units.
12. The method of claim 1 , wherein the first semiconductor chip and the second semiconductor chip are identical.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 30, 2014
October 27, 2015
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