Image transform zero coefficient selection and zero-skip transmission for arbitrary shape transform coding

1. An apparatus comprising: a memory; a processor coupled to the memory and configured to: extract a video object having an arbitrary shape from an image and then divide the video object into blocks; generate a rectangular block of transform coefficients comprising applying a discrete separable unitary transform to a rectangular boundary block of the video object as extracted and divided, wherein the transform coefficients comprise a number of zero-valued transform coefficients greater than or equal to a number of masked pixels, and wherein the transform coefficients comprise at least one non-zero-valued transform coefficient; and generate an encoded output comprising compressing only the non-zero-valued transform coefficients, wherein a number of non-zero-valued transform coefficients is equal to a number of unmasked pixels in the boundary block, and wherein a number of zero-valued transform coefficients is equal to a number of masked pixels in the boundary block, wherein the boundary block has a symmetric size, wherein each pixel in the boundary block is either a masked pixel or an unmasked pixel, wherein each set of pixels is a row or a column of the boundary block, wherein each set of pixels comprises sequentially pixels at a first, a second, a third, and a fourth locations, wherein, when a set comprises two masked pixels and two unmasked pixels, the processor is further configured to: rearrange the set and assign two values to the two masked pixels such that an even sequence is created and generate two non-zero transform coefficients based on the even sequence when the two masked pixels are at the first and the fourth locations or at the second and third locations; and assign two values to the two masked pixels such that an even sequence is created and generate two non-zero transform coefficients based on the even sequence when the two masked pixels are at the first and the second locations, or at the first and the third locations, or at the second and the fourth locations, or at the third and fourth locations.

2. The apparatus of claim 1 , wherein the discrete separable unitary transform is a Discrete Cosine Transform (DCT).

3. The apparatus of claim 1 , wherein a position of at least one zero-valued coefficient in the rectangular block of transform coefficients is determined based on a binary mask corresponding to the video object.

4. The apparatus of claim 2 , wherein the non-zero-valued transform coefficients are read out of the rectangular block of transform coefficients in a pre-defined order to create a sequence of non-zero-valued transform coefficients prior to compression.

5. The apparatus of claim 4 , wherein the zero-valued coefficients are skipped during the reading out of the rectangular block of transform coefficients.

6. The apparatus of claim 5 , wherein, for each row or column of the boundary block, the processor is further configured to: assign values to the masked pixels or rearrange the row or column and assign values to the masked pixels when the row or column comprises a number of masked pixels at pre-defined locations; and generate a number of non-zero-valued DCT coefficients that is less than or equal to the number of unmasked pixels in the row or column a by performing a 1D DCT on the row or column, wherein the remaining DCT coefficients are zero-valued.

7. The apparatus of claim 6 , wherein the rectangular boundary block has a size of 4×4, and wherein the rectangular block of transform coefficients has a size of 4×4.

8. The apparatus of claim 6 , wherein the rectangular boundary block has a size of 8×8, and wherein the rectangular block of transform coefficients has a size of 8×8.

9. The apparatus of claim 1 , wherein the number of zero-valued transform coefficients is greater than or equal to the number of masked pixels.

10. A method comprising: extracting, by a processor, a video object having an arbitrary shape from an image and dividing the video object into blocks; generating, by the processor, a rectangular block of transform coefficients comprising applying a discrete separable unitary transform to a rectangular boundary block of the video object as extracted and divided, wherein the transform coefficients comprise a number of zero-valued transform coefficients greater than or equal to a number of masked pixels, and wherein the transform coefficients comprise at least one non-zero-valued transform coefficient; and generating an encoded output comprising compressing only the non-zero-valued transform coefficients, wherein a number of non-zero-valued transform coefficients is equal to a number of unmasked pixels in the boundary block, and wherein a number of zero-valued transform coefficients is equal to a number of masked pixels in the boundary block, wherein the boundary block has a size of 4×4, wherein each pixel in the boundary block is either a masked pixel or an unmasked pixel, wherein each set of pixels is a row or a column of the boundary block, wherein each set of pixels comprises sequentially four pixels at a first, a second, a third, and a fourth locations, wherein, when a set comprises two masked pixels and two unmasked pixels, the method further comprises: rearranging, by the processor, the set and assign two values to the two masked pixels such that an even sequence is created and generate two non-zero transform coefficients based on the even sequence when the two masked pixels are at the first and the fourth locations or at the second and third locations; and assigning, by the processor, two values to the two masked pixels such that an even sequence is created and generate two non-zero transform coefficients based on the even sequence when the two masked pixels are at the first and the second locations, or at the first and the third locations, or at the second and the fourth locations, or at the third and fourth locations.

11. The method of claim 10 , wherein the discrete separable unitary transform is a Discrete Cosine Transform (DCT).

12. The method of claim 10 , wherein a position of at least one zero-valued coefficient in the rectangular block of transform coefficients is determined based on a binary mask corresponding to the video object.

13. The method of claim 11 , wherein the non-zero-valued transform coefficients are read out of the rectangular block of transform coefficients in a pre-defined order to create a sequence of non-zero-valued transform coefficients prior to compression.

14. The method of claim 13 , wherein the zero-valued coefficients are skipped during the reading out of the rectangular block of transform coefficients.

15. The method of claim 14 further comprising, for each row or column of the boundary block, assigning values to the masked pixels or rearranging the row or column and assigning values to the masked pixels when the row or column comprises a number of masked pixels at pre-defined locations; and generating a number of non-zero-valued DCT coefficients that is less than or equal to the number of unmasked pixels in the row or column a by performing a 1D DCT on the row or column, wherein the remaining DCT coefficients are zero-valued.

16. The method of claim 15 , wherein the rectangular boundary block has a size of 4×4, and wherein the rectangular block of transform coefficients has a size of 4×4.

17. The method of claim 15 , wherein the rectangular boundary block has a size of 8×8, and wherein the rectangular block of transform coefficients has a size of 8×8.

18. The method of claim 10 , wherein the number of zero-valued transform coefficients is greater than or equal to the number of masked pixels.

19. An apparatus for encoding a rectangular boundary block of a video object, wherein the boundary block comprises a plurality of pixels, wherein at least one pixel is a masked pixel and at least one pixel is an unmasked pixel, the apparatus comprising: a processor configured, for each of a plurality of sets of pixels of the boundary block, to: assign a discrete cosine transform (DCT) coefficient a value of zero when the masked and unmasked pixels in a set are arranged in one of a plurality of predefined orders; perform a one-dimensional (1D) DCT on the set to generate a non-zero-valued DCT coefficient when the masked and unmasked pixels in a set are not arranged in one of a plurality of predefined orders; and generate an encoded output comprising compressing only the non-zero-valued DCT coefficients, wherein a number of non-zero-valued DCT coefficients is equal to a number of unmasked pixels in the boundary block, and wherein a number of zero-valued DCT coefficients is equal to a number of masked pixels in the boundary block, wherein the boundary block has a size of 4×4, wherein each pixel in the boundary block is either a masked pixel or an unmasked pixel, wherein each set of pixels in the plurality of sets is a row or a column of the boundary block, wherein each set of pixels comprises sequentially four pixels at a first, a second, a third, and a fourth locations, wherein, when a set comprises two masked pixels and two unmasked pixels, the processor is further configured to: rearrange the set and assign two values to the two masked pixels such that an even sequence is created and generate two non-zero DCT coefficients by performing a 1D DCT on the even sequence when the two masked pixels are at the first and the fourth locations or at the second and third locations; and assign two values to the two masked pixels such that an even sequence is created and generate two non-zero DCT coefficients by performing a 1D DCT on the even sequence when the two masked pixels are at the first and the second locations, or at the first and the third locations, or at the second and the fourth locations, or at the third and fourth locations.

20. The apparatus of claim 19 , wherein the processor is further configured to: assign the three masked pixels equal the value of the unmasked pixel when a set comprises three masked pixels and one unmasked pixel; and generate one non-zero DCT coefficient by performing a 1D DCT on the resulting pixel values.

21. The apparatus of claim 19 , wherein the processor is further configured to: assign the masked pixel a value, denoted as x3, that satisfies the equation x0−x1−x2+x3=0 when a set comprises three unmasked pixels, denoted with values x0, x1, and x2, and one masked pixel, and generate three non-zero DCT coefficients by performing a 1D DCT on the resulting pixel values.

22. The apparatus of claim 19 , wherein the boundary block has a size of 8×8, wherein each pixel in the boundary block is either a masked pixel or an unmasked pixel, wherein each set of pixels in the plurality of sets is a row or a column of the boundary block, wherein each set of pixels comprises sequentially eight pixels at a first, a second, a third, a fourth, a fifth, a sixth, a seventh, and an eighth locations, wherein the processor is further configured to: assign the masked pixel a value, denoted as x7, that satisfies the equation x0−x1−x2+x3+x4−x5−x6+x7=0 when a set comprises seven unmasked pixels, denoted with values x0, x1, x2, x3, x4, x5, x6, and one masked pixel, and generate seven non-zero DCT coefficients by performing a 1D DCT on the resulting pixel values.

23. The apparatus of claim 22 , wherein, when a set comprises six unmasked pixels, denoted with values x0, x1, x2, x3, x4, and x5, and two masked pixels, the processor is further configured to: assign the two masked pixel two values, denoted as x6 and x7, that satisfy two equations −x1+x2+x5−x6=0 and x0−x3−x4+x7=0 when one masked pixel is at the first, fourth, fifth or eighth location, and the other masked pixel is at the second, third, fourth, or seventh location; generate six non-zero DCT coefficients by performing a 1D DCT on the resulting pixel values; rearrange the set such that one masked pixel is at the first, fourth, fifth or eighth location, and the other masked pixel is at the second, third, fourth, or seventh location when one masked pixel is not at the first, fourth, fifth or eighth location, and the other masked pixel is not at the second, third, fourth, or seventh location; assign the two masked pixel two values, denoted as x6 and x7, that satisfy two equations −x1+x2+x5−x6=0 and x0−x3−x4+x7=0 when one masked pixel is at the first, fourth, fifth or eighth location, and the other masked pixel is at the second, third, fourth, or seventh location; and generate six non-zero DCT coefficients by performing a 1D DCT on the resulting pixel values.

24. The apparatus of claim 23 , wherein, when a set comprises five unmasked pixels, denoted with values x0, x1, x2, x3, and x4, and three masked pixels and at least one masked pixel is at the first, fourth, fifth and eighth location, at least one other masked pixel is at the second, third, fourth, or seventh location, and any two of the three masked pixels do not occupy any of location pairs {first, eighth}, {second, seventh}, {third, sixth}, and {fourth, fifth}, the processor is further configured to: assign the three masked pixel three values, denoted as x5, x6, and x7, that satisfy three equations x0−x1−x2+x3+x4−x5−x6+x7=0, −x1+x2+x5−x6=0, and x0−x3−x4+x7=0; generate five non-zero DCT coefficients by performing a 1D DCT on the resulting pixel values; rearrange the set such that at least one masked pixel is at the first, fourth, fifth and eighth location, at least one other masked pixel is at the second, third, fourth, or seventh location, and any two of the three masked pixels do not occupy any of location pairs {first, eighth}, {second, seventh}, {third, sixth}, and {fourth, fifth}; assign the two masked pixel two values, denoted as x6 and x7, that satisfy two equations −x1+x2+x5−x6=0 and x0−x3−x4+x7=0; and generate five non-zero DCT coefficients by performing a 1D DCT on the resulting pixel values.

25. The apparatus of claim 24 , wherein, when a set comprises four unmasked pixels and four masked pixels, the processor is further configured to: assign the four masked pixel four values such that an eight-pixel even sequence is created or rearrange the set and assign the four masked pixel four values such that an eight-pixel even sequence is created; and generate four non-zero DCT coefficients by performing a 1D DCT on the resulting pixel values.

26. The apparatus of claim 25 , wherein, when a set comprises three unmasked pixels, denoted with values x0, x1, and x2, and five masked pixels, the processor is further configured to: assign three masked pixel values such that an even eight-pixel sequence is created, where the two remaining masked pixels are paired in a symmetric pattern or rearrange the set and assign three masked pixel values such that an even eight-pixel sequence is created, where the two remaining masked pixels are paired in a symmetric pattern; compute the value of the two remaining paired pixels as x3, such that x3 satisfies the equation: x0−x1−x2+x3=0; and generate three non-zero DCT coefficients by performing a 1D DCT on the resulting pixel values.

27. The apparatus of claim 25 , wherein, when a set comprises two unmasked pixels and six masked pixels, the processor is further configured to: assign the six masked pixel six values such that two four-pixel even sequences are created or rearrange the set and assign the six masked pixel six values such that two four-pixel even sequences are created; and generate two non-zero DCT coefficients by performing a 1D DCT on the resulting pixel values.

28. The apparatus of claim 26 , wherein, when a set comprises one unmasked pixel and seven masked pixel, the processor is further configured to assign the seven masked pixels equal the value of the unmasked pixel and generate one non-zero DCT coefficient by performing a 1D DCT on the resulting pixel values.