Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a first fin partially surrounded by a first isolation structure and protruding through a top surface thereof. The semiconductor device also includes a second fin partially surrounded by a second isolation structure and protruding through a top surface thereof. The top surface of the first isolation structure is higher than the top surface of the second isolation structure such that the second fin has a height higher than that of the first fin. The second isolation structure has a dopant concentration higher than that of the first isolation structure.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device, comprising: a first fin partially surrounded by a first isolation structure and protruding through a top surface thereof; and a second fin partially surrounded by a second isolation structure and protruding through a top surface thereof, wherein the top surface of the first isolation structure is higher than the top surface of the second isolation structure such that the second fin has a height higher than that of the first fin, and wherein the second isolation structure has a dopant concentration higher than that of the first isolation structure.
2. The semiconductor device structure as claimed in claim 1 , wherein the second isolation structure comprises at least one dopant that is not included in the first isolation structure.
3. The semiconductor device structure as claimed in claim 2 , wherein the at least one dopant comprises As, P, B, BF 2 , Ar, Sb, Ge, Se, N, C, H, or a combination thereof.
4. The semiconductor device structure as claimed in claim 2 , wherein a dopant included in the first isolation structure comprises B, BF 2 , Ge, P, As, N or a combination thereof.
5. The semiconductor device structure as claimed in claim 1 , wherein the height difference of the first fin and the second fin protruding through the top surfaces of the first and second isolation structures, respectively, is in a range from about 5 nm to about 50 nm.
6. The semiconductor device structure as claimed in claim 1 , wherein the first isolation structure comprises the same dopant as the second isolation structure.
7. The semiconductor device structure as claimed in claim 6 , further comprising a gate structure across the first fin and the second fin.
8. The semiconductor device structure as claimed in claim 7 , wherein the gate structure comprises a gate dielectric layer, a gate electrode layer, and/or one or more additional layers.
9. The semiconductor device structure as claimed in claim 8 , wherein the gate electrode layer comprises silicon dioxide or a high-k dielectric layer.
10. The semiconductor device structure as claimed in claim 9 , wherein the high-k dielectric layer comprises hafnium oxide (HfO 2 ).
11. The semiconductor device structure as claimed in claim 9 , wherein the high-k dielectric layer comprises LaO, AlO, ZrO, TiO, Ta 2 O 5 , Y 2 O 3 , SrTiO 3 , BaTiO 3 , BaZrO, HfZrO, HfLaO, HMO, HfSiO, HfSiON, HfTiO, LaSiO, AlSiO, (Ba, Sr)TiO 3 , Al 2 O 3 , other suitable high-k dielectric materials, or combinations thereof.
12. The semiconductor device structure as claimed in claim 1 , wherein the first and second isolation structures are made of a dielectric material comprising silicon oxide, high-density plasma (HDP) oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass, a low-k dielectric material, and/or other suitable insulating material.
13. The semiconductor device structure as claimed in claim 12 , wherein each of the first fin and the second fin has a sidewall and a portion of the sidewall is substantially orthogonal to a major surface of the substrate.
14. The semiconductor device structure as claimed in claim 13 , wherein a lower portion of the sidewall is non-orthogonal to the major surface of the substrate.
15. The semiconductor device structure as claimed in claim 1 , wherein the first fin and the second fin are formed in a substrate, wherein the first fin is formed in a first region of the substrate and the second fin is formed in a second region of the substrate.
16. The semiconductor device structure as claimed in claim 15 , wherein the substrate has a depth from about 40 nm to about 80 nm meaning from a top surface of the first fin and the second fin to a major surface of the substrate.
17. The semiconductor device structure as claimed in claim 15 , wherein the substrate comprises a bulk substrate or a top layer of a compound wafer.
18. The semiconductor device structure as claimed in claim 17 , wherein the compound wafer comprises Ge, SiGe, SiC, a III-V material, a II-VI material, or the like.
19. The semiconductor device structure as claimed in claim 18 , wherein the III-V material comprises GaAs, InAs, GaP, InP or InSb.
20. The semiconductor device structure as claimed in claim 18 , wherein the II-VI material comprises ZeSe, ZnS, or the like.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 27, 2013
November 10, 2015
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