A method of operating a variable resistance memory device comprises determining a level of an access voltage based on a number of rows or columns of a cell array, and supplying the access voltage having the determined level to the cell array.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A variable resistance memory device, comprising: a cell array comprising variable resistance memory cells arranged in m rows and n columns, wherein each variable resistance memory cell comprises a bipolar resistance memory material having an asymmetric hysteresis characteristic; and a voltage generator configured to provide the cell array with a driving voltage determined according to the number of rows and the number of columns.
2. The variable resistance memory device of claim 1 , wherein the variable resistance memory cells are formed without selection elements between word lines and bit lines.
3. The variable resistance memory device of claim 1 , wherein the voltage generator supplies a program voltage to a word line of a selected memory cell in a program operation, the program voltage having a magnitude satisfying a condition of Vrst≦Vpgm<2×Vrst or Vrst≦Vpgm<−(m+n−1)Vset, wherein Vpgm represents the program voltage, Vrst represents a voltage at which a variable resistance memory cell transitions to a reset state from a set state, and Vset represents a voltage at which the variable resistance memory cell transitions from the reset state to the set state.
4. The variable resistance memory device of claim 3 , wherein the voltage generator provides an inhibit voltage corresponding to half the program voltage to a word line of an unselected memory cell in the program operation.
5. The variable resistance memory device of claim 3 , wherein the voltage generator supplies a sensing voltage to a word line of a selected memory cell in a read operation, the sensing voltage having a magnitude satisfying a condition of −(m+n−1)|Vrst|≦Vsen<Vset or Vrst≦Vsen<(m+n−1)|Vset|.
6. The variable resistance memory device of claim 3 , wherein in an erase operation, the voltage generator provides 0V to word lines of selected memory cells and an erase voltage to bit lines of the selected memory cells, wherein the erase voltage is greater than or equal to a voltage of 2×|Vrst|.
7. A method performed in relation to a variable resistance memory device comprising a cell array, the method comprising: determining a level of an access voltage based on a number of rows or columns of the cell array; and supplying the access voltage having the determined level to the cell array.
8. The method of claim 7 , wherein the cell array comprises a plurality of variable resistance memory cells connected between a plurality of word lines and a plurality of bit lines, wherein each of the plurality of variable resistance memory cells is connected to a corresponding word line and bit line without an intervening selection element.
9. The method of claim 8 , wherein each variable resistance memory cell comprises a bipolar resistance memory material.
10. The method of claim 9 , wherein the bipolar resistance memory material has an asymmetric hysteresis characteristic.
11. The method of claim 7 , wherein the access voltage is a program voltage used to switch a resistance state of a variable resistance memory cell of the cell array into a reset state being a high resistance state, wherein the program voltage is greater than or equal to twice a reset voltage of the variable resistance memory cell, which is a negative voltage, and less than or equal to the reset voltage, and wherein the resistance state of the variable resistance memory cell transitions to the reset state in response to the reset voltage.
12. The method of claim 7 , wherein the access voltage is a program voltage used to switch a resistance state of a variable resistance memory cell of the cell array into a reset state, wherein the program voltage is greater than −(m+n−1) times a set voltage of the variable resistance memory cell and lower than a reset voltage of the variable resistance memory cell and a resistance state of the variable resistance memory cell transitions to a set state being a low resistance state in response to the set voltage, wherein m indicates the number of rows of the cell array and n indicates the number of columns of the cell array, wherein the resistance state of the variable resistance memory cell transitions to the reset state being a high resistance state in response to the reset voltage.
13. The method of claim 7 , wherein the access voltage is an erase voltage used to switch a resistance state of a variable resistance memory cell of the cell array into a set state, the erase voltage being higher than a set voltage of the variable resistance memory cell or higher than twice an absolute value of a reset voltage of the variable resistance memory cell, wherein the resistance state of the variable resistance memory cell transitions to the set state being a low resistance state in response to the set voltage and to a reset state being a high resistance state in response to the reset voltage.
14. The method of claim 7 , wherein the access voltage is a sensing voltage used to sense a resistance value of a variable resistance memory cell of the cell array, the sensing voltage is greater than −(m+n−1) times an absolute value of a reset voltage of the variable resistance memory cell and lower than a set voltage of the variable resistance memory cell, wherein a resistance state of the variable resistance memory cell transitions to a high resistance state from a low resistance state in response to the reset voltage and to the low resistance state from the high resistance state in response to the set voltage, wherein m indicates the number of rows and n indicates the number of columns of the cell array.
15. The method of claim 7 , wherein the access voltage is a sensing voltage used to sense a resistance value of a variable resistance memory cell of the cell array, the sensing voltage being higher than a reset voltage of the variable resistance memory cell and lower than (m+n−1) times a set voltage of the variable resistance memory cell, wherein a resistance state of the variable resistance memory cell transitions to a high resistance state from a low resistance state in response to the reset voltage and to the low resistance state from the high resistance state in response to the set voltage, wherein m indicates the number of rows and n indicates the number of columns of the cell array.
16. A variable resistance memory device, comprising: a cell array comprising variable resistance memory cells arranged in rows and columns connected to corresponding word lines and bit lines; a voltage generator configured to control the variable resistance memory cells using operating voltages determined according to the number of rows and the number of columns, wherein each of the variable resistance memory cells comprises a variable resistance storage element connected to a corresponding word line and a corresponding bit line without an intervening selection element.
17. The variable resistance memory device of claim 16 , wherein the operating voltages include a program voltage, and a magnitude of the program voltage is determined according to an inequality Vrst≦Vpgm<2×Vrst or Vrst≦Vpgm<−(m+n−1)Vset, wherein m and n represent the number of rows and columns, respectively, Vpgm represents the program voltage, Vrst represents a voltage at which a variable resistance memory cell transitions to a reset state from a set state, and Vset represents a voltage at which the variable resistance memory cell transitions from the reset state to the set state.
18. The variable resistance memory device of claim 17 , wherein the operating voltages include a program inhibit voltage corresponding to half the program voltage.
19. The variable resistance memory device of claim 16 , wherein the operating voltages include a sensing voltage having a magnitude determined according to an inequality−(m+n−1)|Vrst|≦Vsen<Vset or Vrst≦Vsen<(m+n−1)|Vset|, wherein m and n represent the number of rows and columns, respectively, Vrst represents a voltage at which a variable resistance memory cell transitions to a reset state from a set state and Vset represents a voltage at which the variable resistance memory cell transitions to the set state from the reset state.
20. The device of claim 16 , wherein when one of the variable resistance memory cells that is addressed by a selected one of the word lines and a selected one of the bit lines is programmed to have a high resistance value, the voltage generator: applies a programming voltage to the selected word line, applies an inhibit voltage to all of the word lines other than the selected word line, applies a voltage ground to the selected bit line, and floats all of the bit lines other than the selected bit line so that a current does not flow through the entire bit line.
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December 4, 2012
November 17, 2015
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