Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An electronic device, comprising: a field programmable gate array (FPGA) comprising a set of programmable interconnect arrays having a set of first contacts and a set of second contacts, at least one of the set of first contacts being electrically connected to or electrically disconnected from at least one of the set of second contacts by a programmable configuration cell; a command interface configured to receive an instruction pertaining to activation or deactivation of the programmable configuration cell; and a controller configured to control the programmable configuration cell via one or more inputs in response to receipt of the instruction at the command interface and processing of the command, the controller is further configured to: activate a program circuit configured to enable or disable a programming input to the programmable configuration cell in response to the command interface receiving the instruction pertaining to activation of the programmable configuration cell; apply a program voltage to a first contact of the programmable configuration cell; and at least one of: apply about zero volts to a common node of a voltage divider of the programmable configuration cell; or apply the program voltage to the common node of the voltage divider.
2. The electronic device of claim 1 , wherein the controller is further configured to apply the program voltage or the zero volts for a pulse time configured to change a state of the programmable configuration cell.
3. The electronic device of claim 1 , wherein the controller is further configured to deactivate the program circuit thereby disabling the programming input to the programmable configuration cell, in response to applying the program voltage or about zero volts.
4. The electronic device of claim 1 , wherein the programming input is exclusive to the programmable configuration cell.
5. The electronic device of claim 1 , wherein the first contact of the programmable configuration cell is a first terminal of a pull up resistor of the voltage divider.
6. The electronic device of claim 1 , wherein the controller is further configured to apply about zero volts to a second contact of the programmable configuration cell.
7. The electronic device of claim 6 , wherein the second contact of the programmable configuration cell is a first terminal of a pull down resistor of the voltage divider.
8. The electronic device of claim 1 , wherein the programming input facilitates application of a bias voltage to the common node of the voltage divider independent of a state of resistive components of the voltage divider.
9. The electronic device of claim 1 , wherein the common node of the voltage divider is a second terminal of a pull up resistor of the voltage divider, and is a second terminal of a pull down resistor of the voltage divider.
10. A method of operating a field programmable gate array (FPGA), comprising: receiving a programming instruction identifying a configuration cell of the FPGA for programming; activating programming circuits for a row of the FPGA that comprises the configuration cell, wherein respective ones of the programming circuits are configured to electrically connect respective programming inputs to respective common nodes of respective voltage dividers on the row of the FPGA; applying a programming signal to one of the programming inputs that is connected to the configuration cell; and applying an inhibiting signal to at least one other of the programming inputs that is connected to another configuration cell on the row of the FPGA, wherein the combination of the row of the FPGA and the one of the programming inputs is exclusive within the FPGA to the configuration cell.
11. The method of claim 10 , wherein activating the programming circuits further comprises applying a positive voltage to a first terminal of a pull-up component of one of the voltage dividers that is associated with the configuration cell.
12. The method of claim 10 , wherein activating the programming circuits further comprises applying a positive voltage to respective first terminals of respective pull-up components of the voltage dividers on the row of the FGPA.
13. The method of claim 10 , wherein activating the programming circuits further comprises applying about zero volts to a first terminal of a pull-down component of one of the voltage dividers that is associated with the configuration cell.
14. The method of claim 10 , wherein activating the programming circuits further comprises applying about zero volts to respective first terminals of respective pull-down components of the voltage dividers on the row of the FPGA.
15. The method of claim 10 , further comprising applying the inhibiting signal to each of the respective programming inputs other than the one of the programming inputs that is connected to the configuration cell.
16. The method of claim 10 , further comprising applying the inhibiting signal to programming circuits of a second row of the FPGA.
17. The method of claim 10 , further comprising applying the inhibiting signal to programming circuits of each row of the FPGA other than the row of the FPGA that comprises the configuration cell.
18. A method of operating a field programmable gate array (FPGA), comprising: receiving an erase instruction identifying a configuration cell of the FPGA for erase; activating programming circuits for a row of the FPGA comprising the configuration cell, wherein respective ones of the programming circuits facilitate electrical connection of respective programming inputs to respective voltage dividers of respective configuration cells of the row of the FPGA; applying an erase voltage to one of the programming inputs associated with the configuration cell; and applying an inhibiting signal to at least one other of the programming inputs associated with another configuration cell on the row of the FPGA.
19. The method of claim 18 , further comprising applying the inhibiting signal to each of the programming inputs on the row of the FPGA other than the one of the program inputs.
20. The method of claim 18 , further comprising applying the inhibit signal to programming circuits of on a second row of the FPGA.
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January 28, 2014
November 17, 2015
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