Integrated circuit for memory and operating method thereof

1. An integrated circuit of a memory, comprising: a first data driving circuit, coupled to a first node, for outputting a first data voltage to the first node, wherein the voltage level of the first node is a first voltage level or a second voltage level; a transmitting transistor coupled between the first node and a second node, wherein a voltage level of the second node is a third voltage level or a fourth voltage level; and a sensing circuit controlled by the voltage level of the second node and coupled to the second node; wherein when the transmitting transistor receives a bias voltage and the voltage level of the first node is the first voltage level, the transmitting transistor makes the voltage level of the second node to be set as the third voltage level, the third voltage level and the first voltage level are corresponding to a same logic state; when the transmitting transistor receives the bias voltage and the voltage level of the first node is the second voltage level, the voltage level of the second node is independent of the voltage level of the first node, and the transmitting transistor blocks transfer of the first data voltage from the first data driving circuit to the second node; when the voltage level of the second node is the fourth voltage level, the sensing circuit generates a current path so that the voltage level of the first node is set to be the first voltage level, and when the voltage level of the second node is the third voltage level, the sensing circuit interrupts the current path.

2. The integrated circuit according to claim 1 , wherein the first data driving circuit comprises: a first latch, for storing the first data voltage in a third node, and storing an inverse first data voltage in a fourth node; a first transistor having a first terminal, a second terminal and a third terminal receiving a first control signal, wherein the first terminal of the first transistor and the second terminal of the first transistor are coupled to the third node and the first node, respectively, and when the first control signal is enabled, the first data voltage stored in the third node is outputted to the first node; and a second transistor having a first terminal, a second terminal and a third terminal receiving a second control signal, wherein the first terminal of the second transistor and the second terminal of the second transistor are coupled to the fourth node and the first node, respectively, and when the second control signal is enabled, the inverse first data voltage stored in the fourth node is outputted to the first node.

3. The integrated circuit according to claim 1 , further comprising: a second data driving circuit, coupled to the first node, for outputting a second data voltage to the first node.

4. The integrated circuit according to claim 3 , wherein the second data driving circuit comprises: a second latch, for storing the second data voltage in a fifth node, and storing an inverse second data voltage in a sixth node; a third transistor having a first terminal, a second terminal and a third terminal receiving a third control signal, wherein the first terminal of the third transistor and the second terminal of the third transistor are coupled to the fifth node and the first node, respectively, and when the third control signal is enabled, the second data voltage stored in the fifth node is outputted to the first node; and a fourth transistor having a first terminal, a second terminal and a third terminal receiving a fourth control signal, wherein the first terminal of the fourth transistor and the second terminal of the fourth transistor are coupled to the sixth node and the first node, respectively, and when the fourth control signal is enabled, the inverse second data voltage stored in the sixth node is outputted to the first node.

5. The integrated circuit according to claim 3 , further comprising: a program circuit, comprising: a fifth transistor having a first terminal, a second terminal and a third terminal, wherein the first terminal of the fifth transistor receives the first data voltage, the second terminal of the fifth transistor is coupled to a seventh node, and the third terminal of the fifth transistor receives the inverse first data voltage; a sixth transistor having a first terminal, a second terminal and a third terminal, wherein the first terminal of the sixth transistor receives the second data voltage, the second terminal of the sixth transistor is coupled to the seventh node, and the third terminal of the sixth transistor receives the inverse second data voltage; a seventh transistor having a first terminal, a second terminal and a third terminal, wherein the first terminal of the seventh transistor receives the first data voltage, the second terminal of the seventh transistor is coupled to the seventh node, and the third terminal of the seventh transistor receives the inverse second data voltage; and a eighth transistor having a first terminal, a second terminal and a third terminal receiving a program control signal, wherein the first terminal of the eighth transistor and the second terminal of the eighth transistor are coupled to the seventh node and the second node, respectively.

6. The integrated circuit according to claim 3 , wherein in a setting time period of a program verify operation, the transmitting transistor receives the bias voltage, a target memory cell receives a verify voltage and selectively discharges the second node, the target memory cell is coupled to the second node through a bit line; wherein the verify voltage is corresponding to a verify data, when a set of storing data corresponding to the first data voltage and the second data voltage stored in the first data driving circuit and the second data driving circuit is consistent with the verify data corresponding to the verify voltage, the voltage level of the first node is set to be the second voltage level; wherein when the set of storing data corresponding to the first data voltage and the second data voltage is not consistent with the verify data corresponding to the verify voltage, the voltage level of the first node is set to be the first voltage level.

7. The integrated circuit according to claim 6 , wherein when the second node is discharged, the voltage level of the second node is the third voltage level, when the second node is charged, the voltage level of the second node is the fourth voltage level.

8. The integrated circuit according to claim 7 , wherein the first voltage level and the third voltage level correspond to a first digital value, and the second voltage level and the forth level correspond to a second digital value.

9. The integrated circuit according to claim 1 , wherein the transmitting transistor is an N-type metal-oxide semiconductor field transistor.

10. The integrated circuit according to claim 9 , wherein the value of the bias voltage is between a threshold voltage of the transmitting transistor and twice the threshold voltage of the transmitting transistor.

11. The integrated circuit according to claim 1 , wherein the transmitting transistor is a P-type metal-oxide semiconductor field transistor.

12. An integrated circuit of a memory, comprising: a first data driving circuit, coupled to a first node, for outputting a first data voltage to the first node, wherein the logic level of the first node is a first logic level or a second logic level; and a transmitting transistor coupled between the first node and a second node, wherein a logic level of the second node is a third logic level or a fourth logic level; wherein when the transmitting transistor receives a bias voltage and the logic level of the first node is the first logic level, the transmitting transistor makes the logic level of the second node to be set as the third logic level, the third logic level is equal to the first logic level, when the transmitting transistor receives the bias voltage and the logic level of the first node is the second logic level, the logic level of the second node is independent of the logic level of the first node, and the transmitting transistor blocks transfer of the first data voltage from the first data driving circuit to the second node; wherein the integrated circuit further comprises: a sensing circuit controlled by the logic level of the second node and coupled to the second node; wherein when the logic level of the second node is the fourth logic level, the sensing circuit generates a current path so that the logic level of the first node is set to be the first logic level, and when the logic level of the second node is the third logic level, the sensing circuit interrupts the current path.

13. A operating method of an integrated circuit comprising: providing an integrated circuit, wherein the integrated circuit comprises a first data driving circuit and a transmitting transistor, the first data driving circuit, coupled to a first node, outputs a first data voltage to the first node, the voltage level of the first node is a first voltage level or a second voltage level, the transmitting transistor is coupled between the first node and a second node, a voltage level of the second node is a third voltage level or a fourth voltage level; when the transmitting transistor receives a bias voltage and the voltage level of the first node is the first voltage level, setting the voltage level of the second node to be the third voltage level by the transmitting transistor; and when the transmitting transistor receives the bias voltage and the voltage level of the first node is the second voltage level, making the voltage level of the second node to be independent of the voltage level of the first node, and blocking transfer of the first data voltage from the first data driving circuit to the second node; wherein the integrated circuit further comprises a sensing circuit, the sensing circuit is controlled by the voltage level of the second node and coupled to the second node, the method further comprises: when the voltage level of the second node is the fourth voltage level, generating a current path to set the voltage level of the first node to be the first voltage level by the sensing circuit; and when the voltage level of the second node is the third voltage level, interrupting the current path by the sensing circuit.

14. The operating method according to claim 13 , wherein the integrated circuit further comprises a second data driving circuit, the second data driving circuit is coupled to the first node, the method further comprises: outputting a second data voltage to the first node by the second data driving circuit.

15. The operating method according to claim 14 , wherein the second node is coupled to a target memory cell through a bit line, the method further comprises: in a setting time period of a program verify operation, providing the bias voltage to the transmitting transistor, and providing a verify voltage to the target memory cell to selectively discharge the second node; wherein the verify voltage is corresponding to a verify data, when a set of storing data corresponding to the first data voltage and the second data voltage stored in the first data driving circuit and the second data driving circuit is consistent with the verify data corresponding to the verify voltage, setting the voltage level of the first node to be the second voltage level; wherein when the set of storing data corresponding to the first data voltage and the second data voltage is not consistent with the verify data corresponding to the verify voltage, the voltage level of the first node is set to be the first voltage level.

16. The operating method according to claim 15 , wherein when the second node is discharged, the voltage level of the second node is the third voltage level, when the second node is charged, the voltage level of the second node is the fourth voltage level.

17. The operating method according to claim 13 , wherein the transmitting transistor is an N-type metal-oxide semiconductor field transistor.

18. The operating method according to claim 17 , wherein the value of the bias voltage is between a threshold voltage of the transmitting transistor and twice the threshold voltage of the transmitting transistor.