A semiconductor memory apparatus includes a command processing block configured to generate a voltage generation start signal, a first write control signal, a second write control signal, a read signal, and an operation signal in response to a first control signal and a second control signal in a write operation, and a memory control block configured to electrically couple a memory block, which stores data, to a sense amplifier or apply a predetermined voltage to the memory block in response to the voltage generation start signal, the first write control signal, the second write control signal, the read signal, and the operation signal.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor memory apparatus comprising: a command processing block configured to generate a voltage generation start signal, a first write control signal, a second write control signal, a read signal, and an operation signal in response to a first control signal and a second control signal in a write operation; and a memory control block configured to electrically couple a memory block, which stores data, to a sense amplifier or apply a predetermined voltage to the memory block in response to the voltage generation start signal, the first write control signal, the second write control signal, the read signal, and the operation signal.
2. The semiconductor memory apparatus according to claim 1 , wherein the command processing block enables the read signal and the operation signal in response to an internal command signal in a read operation.
3. The semiconductor memory apparatus according to claim 2 , wherein, in the write operation, the command processing block enables the voltage generation start signal in response to the internal command signal, generates the read signal that is enabled for a predetermined time when the voltage generation start signal is enabled, and selectively enables the first and second write control signals in response to the first and second control signals when the read signal is disabled, in the read operation, the command processing block enables the read signal in response to the internal command signal, and when one of the voltage generation start signal and the read signal is enabled, the command processing block enables the operation signal.
4. The semiconductor memory apparatus according to claim 3 , wherein, when the read signal and the operation signal are enabled, the memory control block electrically couples the memory block to the sense amplifier, and when the voltage generation start signal is enabled, the memory control block starts to generate a voltage to be supplied to the memory block, and applies the voltage having a predetermined voltage level to the memory block in response to the first and second write control signals and the operation signal.
5. The semiconductor memory apparatus according to claim 4 , wherein the memory control block comprises: a first switch configured to electrically couple the memory block to a common node in response to the operation signal; a second switch configured to electrically couple the common node to the sense amplifier in response to the read signal; and a voltage supply unit configured to start voltage generation in response to the voltage generation start signal, and apply the predetermined voltage to the common node in response to the first and second write control signals.
6. The semiconductor memory apparatus according to claim 5 , wherein the voltage supply unit comprises: a first memory voltage applying section configured to generate a first voltage for writing when the voltage generation start signal is enabled, and apply a first memory voltage corresponding to a voltage level of the first voltage for writing to the common node in response to the first write control signal; and a second memory voltage applying section configured to generate a second voltage for writing when the voltage generation start signal is enabled, and apply a second memory voltage corresponding to a voltage level of the second voltage for writing to the common node in response to the second write control signal.
7. The semiconductor memory apparatus according to claim 6 , wherein the voltage generation start signal has a phase substantially equal to that of the voltage generation start signal in the write operation.
8. The semiconductor memory apparatus according to claim 6 , wherein the first memory voltage applying section comprises: a voltage supply section for writing configured to be activated when the voltage generation start signal is enabled, and generate the first voltage for writing; a transistor for voltage generation configured to generate the first memory voltage in correspondence with a voltage level of the first voltage for writing; and a third switch configured to apply the first memory voltage to the common node in response to the first write control signal.
9. The semiconductor memory apparatus according to claim 8 , wherein the transistor for voltage generation receives the first voltage for writing through a gate thereof, receives a driving voltage through a source thereof, and outputs the first memory voltage through a drain thereof.
10. The semiconductor memory apparatus according to claim 9 , wherein the first voltage has a voltage level substantially equal to a voltage level of the first memory voltage.
11. The semiconductor memory apparatus according to claim 6 , wherein the second memory voltage applying section comprises: a voltage supply section for writing configured to be activated when the voltage generation start signal is enabled, and generate the second voltage for writing; a transistor for voltage generation configured to generate the second memory voltage in correspondence with a voltage level of the second voltage for writing; and a third switch configured to apply the second memory voltage to the common node in response to the second write control signal.
12. The semiconductor memory apparatus according to claim 11 , wherein the transistor for voltage generation receives the second voltage for writing through a gate thereof, receives a driving voltage through a source thereof, and outputs the second memory voltage through a drain thereof.
13. The semiconductor memory apparatus according to claim 12 , wherein the second voltage has a voltage level substantially equal to a voltage level of the second memory voltage.
14. The semiconductor memory apparatus according to claim 1 , wherein the sense amplifier is activated in response to the read signal, and generates storage data in response to data stored in the memory block.
15. The semiconductor memory apparatus according to claim 14 , further comprising: a data comparison block configured to compare input data input from an exterior with the storage data, and generate the first and second control signals.
16. The semiconductor memory apparatus according to claim 15 , wherein the data comparison block disables the first and second control signals when the input data is substantially equal to the storage data, and enables one of the first and second control signals in response to the input data when the input data is different from the storage data.
17. The semiconductor memory apparatus according to claim 3 , wherein the command processing block includes: a write decoder configured for decoding the internal command signal and enabling the voltage generation start signal; a read decoder configured for decoding the internal command signal and enabling a preliminary read signal; a pulse generation unit configured for generating a write pulse in response to the voltage generation start signal; a multiplexer configured for outputting one of the preliminary read signal and the write pulse as the read signal; a control signal generation unit configured for generating the first and second write control signals in response to the voltage generation start signal, the write pulse and the first and second control signals; and an operation signal generation unit configured for generating the operation signal in response to the voltage generation start signal and the read signal.
18. A semiconductor memory apparatus comprising: a memory block configured to store data according to a voltage level of a memory voltage; a voltage supply unit configured to generate the memory voltage when an external command is a write command, and apply the memory voltage to the memory block in response to a control signal; and a data comparison block configured to compare data input from an exterior with storage data, and generate the control signal.
19. The semiconductor memory apparatus according to claim 18 , further comprising: a sense amplifier configured to determine a data value of the memory block and generate the storage data when the external command is the write command.
20. The semiconductor memory apparatus according to claim 19 , wherein, when the external command is the write command, the voltage supply unit generates the memory voltage and simultaneously the sense amplifier compares the input data with the storage data.
21. The semiconductor memory apparatus according to claim 20 , wherein the data comparison block disables the control signal when the input data is substantially equal to the storage data, and enables the control signal when the input data is different from the storage data, and the voltage supply unit applies the memory voltage to the memory block when the control signal is enabled, and does not apply the memory voltage to the memory block when the control signal is disabled.
22. An operation method of a semiconductor memory apparatus, comprising: a step of comparing stored data with input data to generate a control signal and simultaneously generating a memory voltage in a write operation; and a step of applying the memory voltage to the memory block in response to the control signal, and storing data in the memory block.
23. The operation method according to claim 22 , wherein the step of comparing the stored data with the input data to generate the control signal and simultaneously generating the memory voltage in the write operation comprises: a step of electrically coupling the memory block to a sense amplifier and simultaneously generating the memory voltage; and a step of determining, by the sense amplifier, data of the memory block, comparing a determined result with the input data, and generating the control signal.
24. The operation method according to claim 23 , wherein the step of determining, by the sense amplifier, the data of the memory block, comparing the determined result with the input data, and generating the control signal comprises: a step of disabling the control signal when the determined result in the sense amplifier is substantially equal to the input data; and a step of enabling the control signal when the determined result in the sense amplifier is different from the input data.
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September 10, 2013
November 24, 2015
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