Voltage balancing for a memory cell array is provided. One example method of voltage balancing for a memory array can include activating an access node coupled to a row of a memory array to provide voltage to the row of the memory array, activating a stabilizing transistor coupled to the row of the memory array to create a feedback loop, and activating a driving node coupled to a column of the memory array, wherein activating the driving node deactivates the stabilizing transistor once the column reaches a particular voltage potential.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory apparatus, comprising: an array of memory cells, wherein the memory cells are coupled at an intersection of a number of access lines and a number of sense lines of the array; an access device configured to control application of a first voltage, provided by a first power supply, to an access line coupled to an access line in the array to provide a first voltage to the access line utilizing a first power supply; a driving device coupled to a sense line in the array to provide a second voltage to the sense line utilizing a second power supply; and a stabilizing transistor coupled to the access line in the array to react to a change from the first voltage to the second voltage and maintain an intended voltage on the access line utilizing the first power supply when the access device is deactivated.
2. The apparatus of claim 1 , wherein the access device is an nMOS transistor coupled to the first power supply.
3. The apparatus of claim 1 , wherein the stabilizing transistor provides a feedback loop to the access line during an intermediate regime operation on the array.
4. The apparatus of claim 1 , wherein the intermediate regime operation occurs between a pre-charge regime operation and a snap back regime operation for a cross point memory array.
5. The apparatus of claim 1 , wherein the first power supply provides a voltage that is of a different magnitude and bias than the second power supply.
6. The apparatus of claim 1 , wherein the stabilizing transistor remains active in an “ON” state after the access device is switched to an “OFF” state.
7. The apparatus of claim 6 , wherein the stabilizing transistor is switched to an “OFF” state when a snap back regime operation occurs.
8. The apparatus of claim 1 , wherein the stabilizing transistor is deactivated when the driving device applies a particular voltage potential to the bit line.
9. A memory apparatus, comprising: an array of memory cells, wherein the memory cells are coupled at an intersection of a number of access lines of the memory array and a number of sense lines of the memory array; a first transistor coupled to an access line of the memory array and coupled to a first power supply, wherein the first transistor provides a voltage from the first power supply to the access line to pre-charge the access line of the memory array; a second transistor coupled to a sense line of the memory array and coupled to a second power supply, wherein the second transistor provides voltage from the second power supply to the sense line when activated; and a stabilizing transistor coupled to the access line of the memory array and coupled to the first power supply, wherein the stabilizing transistor includes a gate that is coupled to the access line of the memory array, and wherein the stabilizing transistor remains “ON” when the first transistor is deactivated.
10. The apparatus of claim 9 , wherein the stabilizing transistor is activated when the access line is pre-charged.
11. The apparatus of claim 10 , wherein the stabilizing transistor utilizes the first power supply to maintain a charge on the access line of the memory array within a predetermined voltage range when the first transistor is deactivated.
12. The array of claim 10 , wherein the stabilizing transistor creates as a feedback loop for the access line.
13. The array of claim 12 , wherein the feedback loop maintains a charge of the corresponding access line when the charge of the corresponding access line is being altered within a particular range.
14. The array of claim 12 , wherein the feedback loop of the provided by the stabilizing transistors is deactivated when a change in a charge of the corresponding access line exceeds a threshold.
15. A method of memory line stabilization: activating an access device coupled to a row of a memory array to provide voltage to the row of the memory array; activating a stabilizing transistor coupled to the row of the memory array to create a feedback loop, wherein activating the stabilizing transistor includes reacting to a change in voltage to the row of the memory array; and activating a driving device coupled to a column of the memory array, wherein activating the driving device deactivates the stabilizing transistor at a ramped voltage potential.
16. The method of claim 15 , wherein the stabilizing transistor connects the first power supply to the row of the memory array when the row of the memory array is pre-charged to a level that exceeds a threshold voltage of stabilizing transistor.
17. A method of memory line stabilization: activating an access device coupled to an access line of a memory array to connect a first power supply to the access line of the memory array; deactivating the access device coupled to the access line of the memory array when the access line has a particular voltage; activating a stabilizing transistor coupled to the access line of the memory array using the particular voltage on the access line; and activating a driving device coupled to a sense line of the memory array to connect a second power supply to the sense line of the memory array first at a pre-charge voltage potential and then a ramped voltage potential, wherein activating the driving device deactivates the stabilizing transistor at the ramped voltage potential.
18. The method of claim 17 , wherein deactivating the access device provides a demarcation of an intermediate regime of operation in the operation of a cross point memory array architecture.
19. The method of claim 18 , wherein activating the stabilizing transistor activates a feedback loop to maintain the particular voltage during the intermediate regime.
20. The method of claim 18 , wherein the intermediate regime includes a time period between charging the access line of the memory array and activating the driving device.
21. The method of claim 17 , wherein activating the driving device deactivates the stabilizing transistor when conduction through a cell pulls a voltage potential of the access line, and applied to a gate of the s stabilizing transistor, to a more positive potential below a threshold voltage (Vt) of the stabilizing transistor to effectively turns the stabilizing transistor “OFF” during a read regime.
22. The method of claim 17 , wherein activating the stabilizing transistor to maintain the particular voltage of the access line of the memory array includes maintaining a particular gap voltage between the voltage of the access line and a voltage of the sense line.
23. A method of memory line stabilization: activating an access device coupled to a row of a memory array to provide voltage to the row of the memory array, wherein activating the access device includes connecting a first power supply to the row of the memory array to charge the row of the memory array to a particular voltage, wherein the access device is deactivated when the row of the memory array is charged to the particular voltage; activating a stabilizing transistor coupled to the row of the memory array to create a feedback loop; and activating a driving device coupled to a column of the memory array, wherein activating the driving device deactivates the stabilizing transistor at a ramped voltage potential.
24. The method of claim 23 , wherein activating the access device to provide voltage to the row of the memory array activates the stabilizing transistor and provides the feedback loop to the row of the memory array utilizing the first power supply to maintain the particular voltage to the row of the memory array.
25. The method of claim 24 , wherein activating the driving device deactivates the stabilizing transistor in response to the driving device connecting a second power supply to the column of the memory array at the ramped voltage potential.
26. The method of claim 23 , wherein the second power supply provides a greater voltage than the first power supply.
27. A method of memory line stabilization: activating an access device coupled to a row of a memory array to provide voltage to the row of the memory array; activating a stabilizing transistor coupled to the row of the memory array to create a feedback loop, wherein activating the stabilizing transistor includes reacting to a change in voltage to the row of the memory array; and activating a driving device coupled to a column of the memory array, wherein activating the driving device deactivates the stabilizing transistor at a ramped voltage potential and initiates a demarcation of a read operation in the operation of a cross point memory array architecture.
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December 20, 2013
November 24, 2015
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