Sensor amplifier, memory device comprising same, and related method of operation

1. A sense amplifier, comprising: a first PMOS transistor configured to connect a complementary sensing bitline with a line of a first control signal in response to a sensing bitline; a second PMOS transistor configured to connect the sensing bitline with the line of the first control signal in response to the complementary sensing bitline; a first NMOS transistor configured to connect the complementary sensing bitline with a line of a second control signal in response to a bitline; a second NMOS transistor configured to connect the sensing bitline with the line of the second control signal in response to a complementary bitline; a first isolation switch configured to connect the bitline with the sensing bitline in response to an isolation signal; a second isolation switch configured to connect the complementary bitline with the complementary sensing bitline in response to the isolation signal; a first offset cancellation switch configured to connect the bitline with the complementary sensing bitline in response to an offset cancellation signal; and a second offset cancellation switch configured to connect the complementary bitline with the sensing bitline in response to the offset cancellation signal.

2. The sense amplifier of claim 1 , wherein during a precharge operation, the first and second isolation switches are configured to be turned on under control of the isolation signal and the first and second offset cancellation switches are configured to be turned on according to the offset cancellation signal, to precharge the bitline, the complementary bitline, the sensing bitline and the complementary sensing bitline to a precharge voltage.

3. The sense amplifier of claim 1 , wherein during an offset cancellation operation, the first and second isolation switches are configured to be turned off according to the isolation signal, and the first and second offset cancellation switches are configured to be turned on according to the offset cancellation signal to charge or discharge the bitline by an offset due to the first and second PMOS transistors and the first and second NMOS transistors.

4. The sense amplifier of claim 3 , wherein during the offset cancellation operation, the first control signal is an input voltage and the second control signal is a ground voltage.

5. The sense amplifier of claim 1 , wherein during a charge sharing operation, the first and second isolation switches are configured to be turned off according to the isolation signal and the first and second offset cancellation switches are configured to be turned off according to the offset cancellation signal, to charge or discharge the bitline by a predetermined level based on charge sharing of charges of the bitline and charges of a memory cell connected to the bitline.

6. The sense amplifier of claim 5 , further comprising an equalizing circuit configured to charge the sensing bitline and the complementary sensing bitline to a precharge voltage in response to an equalizing signal while the charge sharing operation is performed.

7. The sense amplifier of claim 6 , wherein the equalizing circuit comprises first to third equalizing switches that operate in response to the equalizing signal, wherein the first and second equalizing switches are connected in series between the sensing bitline and the complementary sensing bitline, and wherein the third equalizing switch is connected between the sensing bitline and the complementary sensing bitline.

8. The sense amplifier of claim 1 , wherein during a pre-sensing operation, the first and second isolation switches are configured to be turned off under control of the isolation signal, the first and second offset cancellation switches are configured to be turned off according to control of the offset cancellation signal, the first control signal is an input voltage and the second control signal is a ground voltage to charge or discharge the sensing bitline and the complementary sensing bitline to the input voltage or the ground voltage according to a voltage variation of the bitline.

9. The sense amplifier of claim 1 , wherein during a restoring operation, the first and second isolation switches are configured to be turned on according to control of the isolation signal and the first and second offset cancellation switches are configured to be turned off under control of the offset cancellation signal to store data in a memory cell based on a voltage level of the sensing bitline.

10. A sense amplifier comprising: a first PMOS transistor configured to connect a complementary sensing bitline with a line of a first control signal in response to a sensing bitline; a second PMOS transistor configured to connect the sensing bitline with the line of the first control signal in response to the complementary sensing bitline; a first NMOS transistor configured to connect the complementary sensing bitline with a line of a second control signal in response to a bitline; a second NMOS transistor configured to connect the sensing bitline with a line of a third control signal in response to a complementary bitline; a first isolation switch configured to connect the bitline with the sensing bitline in response to an isolation signal; a second isolation switch configured to connect the complementary bitline with the complementary sensing bitline in response to the isolation signal; a first offset cancellation switch configured to connect the bitline with the complementary sensing bitline in response to an offset cancellation signal; and a second offset cancellation switch configured to connect the complementary bitline with the sensing bitline in response to the offset cancellation signal, wherein the second control signal comprises the third control signal and interconnection resistance noise.

11. A memory device comprising: a memory cell array comprising multiple memory blocks; multiple sense amplifiers configured to be connected to the memory blocks and having an open bitline structure; and a reference voltage unit disposed at an edge area of the memory cell array and connected to sense amplifiers from among the sense amplifiers that are adjacent to the edge area, wherein each of the sense amplifiers comprises a sense amplifying unit configured to be connected to a bitline and a complementary bitline, to sense a voltage change of the bitline in response to first and second control signals, and to control voltages of a sensing bitline and a complementary sensing bitline based on the sensed voltage change; a first isolation switch configured to connect the bitline with the sensing bitline in response to an isolation signal; a second isolation switch configured to connect the complementary bitline with the complementary sensing bitline in response to the isolation signal; a first offset cancellation switch configured to connect the bitline with the complementary sensing bitline in response to an offset cancellation signal; and a second offset cancellation switch configured to connect the complementary bitline with the sensing bitline in response to the offset cancellation signal, and wherein the reference voltage unit comprises multiple capacitors, and wherein the sense amplifiers adjacent to the edge area are configured to charge the capacitors to a precharge voltage.

12. The memory device of claim 11 , wherein during an offset cancelling operation, the sense amplifiers are configured to cut off connection between a respective bitline and a respective sensing bitline and connection between a respective complementary bitline and a respective complementary sensing bitline according to control of the isolation signal and to maintain connection between the respective bitline and the respective complementary sensing bitline and connection between the respective complementary bitline and the respective sensing bitline according to control of the offset cancellation signal, wherein during the offset cancelling operation the respective bitline is charged or discharged by an offset of the sense amplifiers.

13. The memory device of claim 11 , wherein during a pre-sensing operation, the first control signal transitions to an input voltage, the second control signal transitions to a ground voltage, and the sense amplifiers are configured to cut off connection between a respective bitline and a respective sensing bitline and connection between a respective complementary bitline and a respective complementary sensing bitline according to control of the isolation signal and to cut off connection between the respective bitline and the respective complementary sensing bitline and connection between the respective complementary bitline and the respective sensing bitline according to control of the offset cancellation signal, and wherein during the pre-sensing operation, voltage levels of the respective sensing bitline and the respective complementary sensing bitline are amplified or reduced based on a voltage variation of the respective bitline.