Flash-memory low-speed read mode control circuit

1. A flash-memory low-speed read mode control circuit, with a low-speed read mode of a flash memory being a read mode having a read rate less than 30 MHZ, comprising: a charge pump, whose output terminal produces an output voltage when the charge pump is working; an output terminal of the charge pump is connected to a first voltage division circuit, wherein the first voltage division circuit includes a first resistor, a second resistor and a first switch connected in series, a first terminal of the first resistor being connected to an output terminal of the charge pump, a second terminal of the first resistor being connected to a first terminal of the second resistor, the first switch being connected between a second terminal of the second resistor and the ground; when the first switch is turned on, the flash memory is in a data read mode in the low-speed read mode; when the first switch is turned off, the flash memory is in a charge pump electric-leakage mode in the low-speed read mode; in the data read mode, the second terminal of the first resistor outputs a first component voltage of the output voltage, which first component voltage is connected to a positive input terminal of the comparator; a negative input terminal of the comparator is connected to a supply voltage; the output terminal of the comparator is connected to a first input terminal of an NAND gate, with an output terminal of the NAND gate connected to the input terminal of the charge pump through a first buffer; the charge pump works when the input terminal of the charge pump is at a high level, and stops working when the input terminal of the charge pump is at a low level; in the data read mode, the charge pump works when the first component voltage is below the supply voltage, and stops working when the first component voltage is equal to the supply voltage while keeping the output voltage of the charge pump at a stable value that is used as a data-read working voltage; the data-read working voltage is greater than the low threshold voltage of the charge pump in a waiting mode; an output terminal of the charge pump is connected to a second voltage division circuit, which is composed of a first capacitor and a second capacitor interconnected in series, a first terminal of the first capacitor being connected to the output terminal of the charge pump, the second capacitor being connected between a second terminal of the first capacitor and the ground, the second terminal of the first capacitor outputting the second component voltage; a first PMOS transistor, whose source electrode is connected to the supply voltage, a drain electrode of the first PMOS transistor being grounded through a first current source, a gate electrode of the first PMOS transistor being connected to the second component voltage; a proportional relation between the second component voltage and the output voltage is regulated by regulating capacitance of the first capacitor and the second capacitor: when the output voltage is less than or equal to the low threshold voltage of the charge pump, a voltage difference between the supply voltage and the second component voltage is greater than or equal to a threshold voltage of the first PMOS transistor, and makes the first PMOS transistor turned on; when the output voltage is greater than the low threshold voltage of the charge pump, a voltage difference between the supply voltage and the second component voltage is less than a threshold voltage of the first PMOS transistor, and makes the first PMOS transistor turned off; a second NMOS transistor, whose source electrode is grounded, a drain electrode of the second NMOS transistor being connected to the supply voltage through a second current source, a gate electrode of the second NMOS transistor being connected to the drain electrode of the first PMOS transistor; the drain electrode of the second NMOS transistor is connected to a reset terminal of a D flip flop through a second buffer, with this reset terminal resetting the D flip flop at a low level; a D input terminal of the D flip flop is connected to the supply voltage, an input terminal of a clock is connected to an on-chip timing signal, and a Q output terminal is connected to a second input terminal of the NAND gate.

2. The flash-memory low-speed read mode control circuit according to claim 1 , wherein in the charge pump electric-leakage mode, the output voltage of the charge pump starts to decrease from the stable value, with the output voltage of the charge pump made to be always greater than the low threshold voltage in the charge pump electric-leakage mode by setting a difference between the low threshold voltage and the stable value of the output voltage of the charge pump.

3. The flash-memory low-speed read mode control circuit according to claim 2 , wherein the difference between the low threshold voltage and the stable value of the output voltage of the charge pump is 0.3-0.4 V.

4. The flash-memory low-speed read mode control circuit according to claim 1 wherein the stable value of the output voltage of the charge pump is made to be 2.2 times as much as the supply voltage by regulating a value of the first resistor and the second resistor; the low threshold voltage of the charge pump is set to be 2 times as much as the supply voltage.

5. The flash-memory low-speed read mode control circuit according to claim 2 , wherein the stable value of the output voltage of the charge pump is made to be 2.2 times as much as the supply voltage by regulating a value of the first resistor and the second resistor; the low threshold voltage of the charge pump is set to be 2 times as much as the supply voltage.

6. The flash-memory low-speed read mode control circuit according to claim 3 , wherein the stable value of the output voltage of the charge pump is made to be 2.2 times as much as the supply voltage by regulating a value of the first resistor and the second resistor; the low threshold voltage of the charge pump is set to be 2 times as much as the supply voltage.