Patentable/Patents/US-9202889
US-9202889

Method for improving transistor performance through reducing the salicide interface resistance

PublishedDecember 1, 2015
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.

Patent Claims
6 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A method comprising: forming an insulator region on a substrate having a first lattice constant; etching a source region and a drain region in the substrate, thereby defining a channel region located between the source region and the drain region, and beneath the insulator region; depositing a semiconductor material in the source region and in the drain region, the semiconductor material having a second lattice constant larger than the first lattice constant; wherein the semiconductor material in the source region and in the drain region creates compression in the channel region; and forming contacts on the top surface of the semiconductor material in the source region and in the drain region; wherein the contacts comprise an alloy of nickel and the semiconductor material.

2

2. The method of claim 1 wherein the semiconductor material is a silicon germanium alloy.

3

3. The method of claim 2 wherein the contacts comprise nickel silicon germanium silicide.

4

4. The method of claim 2 wherein the silicon germanium alloy has a germanium composition between 5% and 50%.

5

5. The method of claim 4 wherein the silicon germanium alloy has a germanium composition between 10% and 40%.

6

6. The method of claim 5 wherein the silicon germanium alloy has a germanium composition between 15% and 30%.

Classification Codes (CPC)

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Patent Metadata

Filing Date

June 28, 2013

Publication Date

December 1, 2015

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Cite as: Patentable. “Method for improving transistor performance through reducing the salicide interface resistance” (US-9202889). https://patentable.app/patents/US-9202889

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