A semiconductor memory apparatus includes a control signal generation unit configured to generate a control signal according to a mode control signal and a refresh signal; a first sense amplifier driving voltage generation unit configured to generate a first sense amplifier driving voltage according to the control signal, a first sense amplifier enable signal and a switching control signal; a switching control unit configured to generate the switching control signal according to the control signal and a second sense amplifier enable signal; a second sense amplifier driving voltage generation unit configured to generate a second sense amplifier driving voltage according to the second sense amplifier enable signal; and a switching unit configured to electrically couple or decouple output nodes of the first sense amplifier driving voltage generation unit and the second sense amplifier driving voltage generation unit according to the switching control signal.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor memory apparatus comprising: a control signal generation unit configured to generate a control signal according to a mode control signal and a refresh signal; a first sense amplifier driving voltage generation unit configured to generate a first sense amplifier driving voltage according to the control signal, a first sense amplifier enable signal and a switching control signal; a switching control unit configured to generate the switching control signal according to the control signal and a second sense amplifier enable signal; a second sense amplifier driving voltage generation unit configured to generate a second sense amplifier driving voltage according to the second sense amplifier enable signal; and a switching unit configured to electrically couple or electrically decouple an output node of the first sense amplifier driving voltage generation unit and an output node of the second sense amplifier driving voltage generation unit according to the switching control signal.
2. The semiconductor memory apparatus according to claim 1 , wherein the control signal generation unit enables the control signal if the refresh signal is enabled in a state where the mode control signal is enabled, and disables the control signal when a voltage application enable signal is disabled.
3. The semiconductor memory apparatus according to claim 2 , wherein the control signal generation unit comprises: a latch section configured to latch a voltage level of the mode control signal when the refresh signal is enabled and output the control signal, and disable the control signal when a disable pulse is inputted; and a pulse generating section configured to generate the disable pulse when the voltage application enable signal is disabled.
4. The semiconductor memory apparatus according to claim 2 , wherein the first sense amplifier driving voltage generation unit generates the first sense amplifier driving voltage during an enable period of the first sense amplifier enable signal when the control signal is disabled, and wherein the first sense amplifier driving voltage generation unit generates the first sense amplifier driving voltage during a period longer than the enable period of the first sense amplifier enable signal when the control signal is enabled.
5. The semiconductor memory apparatus according to claim 4 , wherein the first sense amplifier driving voltage generation unit comprises: an enable extension signal generating section configured to enable a sense amplifier enable extension signal in response to the first sense amplifier enable signal, and disable the sense amplifier enable extension signal in response to the switching control signal; a signal selecting section configured to output one of the first sense amplifier enable signal and the sense amplifier enable extension signal as the voltage application enable signal in response to the control signal; and a driving voltage applying section configured to generate the first sense amplifier driving voltage during an enable period of the voltage application enable signal.
6. The semiconductor memory apparatus according to claim 5 , wherein the enable extension signal generating section comprises: a delay part configured to delay the switching control signal, and generate a delayed switching control signal; and a latch section configured to enable the sense amplifier enable extension signal and retain an enabled state when the first sense amplifier enable signal is enabled, and disable the sense amplifier enable extension signal when the delayed switching control signal is enabled.
7. The semiconductor memory apparatus according to claim 1 , wherein the switching control unit generates the switching control signal enabled for a predetermined time, when the second sense amplifier enable signal is enabled in a state where the control signal is enabled.
8. The semiconductor memory apparatus according to claim 1 , wherein the switching unit electrically couples the output node of the first sense amplifier driving voltage generation unit and the output node of the second sense amplifier driving voltage generation unit when the switching control signal is enabled, and electrically decouples the output node of the first sense amplifier driving voltage generation unit and the output node of the second sense amplifier driving voltage generation unit when the switching control signal is disabled.
9. A semiconductor memory apparatus comprising: a voltage generation block configured to generate a first sense amplifier driving voltage during an enable period of a first sense amplifier enable signal or to generate the first sense amplifier driving voltage during a period longer than the enable period of the first sense amplifier enable signal, according to a mode control signal and a refresh signal; a second sense amplifier driving voltage generation unit configured to generate a second sense amplifier driving voltage during an enable period of a second sense amplifier enable signal; and a power line control block configured to electrically couple or electrically decouple a power line of a first sense amplifier and a power line of a second sense amplifier according to the second sense amplifier enable signal where the first sense amplifier driving voltage is generated during the period longer than the enable period of the first sense amplifier enable signal.
10. The semiconductor memory apparatus according to claim 9 , wherein the first sense amplifier driving voltage is applied to the first sense amplifier through the power line of the first sense amplifier, and wherein the second sense amplifier driving voltage is applied to the second sense amplifier through the power line of the second sense amplifier.
11. The semiconductor memory apparatus according to claim 9 , wherein the voltage generation block comprises: a control signal generation unit configured to enable a control signal when the mode control signal is enabled and the refresh signal is enabled, and disable the control signal in response to the second sense amplifier enable signal; and a first sense amplifier driving voltage generation unit configured to generate the first sense amplifier driving voltage during the period longer than the enable period of the first sense amplifier enable signal when the control signal is enabled, and generate the first sense amplifier driving voltage during the enable period of the first sense amplifier enable signal when the control signal is disabled.
12. The semiconductor memory apparatus according to claim 11 , wherein the control signal generation unit enables the control signal when mode control signal is enabled and the refresh signal is enabled, and disables the control signal when a voltage application enable signal is disabled.
13. The semiconductor memory apparatus according to claim 12 , wherein the first sense amplifier driving voltage generation unit comprises: an enable extension signal generating section configured to enable a sense amplifier enable extension signal when the first sense amplifier enable signal is enabled, and disable the sense amplifier enable extension signal when a predetermined time passes after a switching control signal is enabled; a signal selecting section configured to output the first sense amplifier enable signal as the voltage application enable signal when the control signal is disabled, and output the sense amplifier enable extension signal as the voltage application enable signal when the control signal is enabled; and a driving voltage applying section configured to generate the first sense amplifier driving voltage during an enable period of the voltage application enable signal.
14. The semiconductor memory apparatus according to claim 13 , wherein the power line control block comprises: a switching control unit configured to generate the switching control signal enabled for the predetermined time, when the second sense amplifier enable signal is enabled in a state where the control signal is enabled; and a switching unit configured to electrically couple or electrically decouple the power line of the first sense amplifier and the power line of the second sense amplifier in response to the switching control signal.
15. A semiconductor memory apparatus comprising: a control signal generation unit configured to enable a control signal when a refresh signal and a mode control signal are enabled, and disable the control signal when a voltage application enable signal is disabled; a first sense amplifier driving voltage generation unit configured to generate the first sense amplifier driving voltage when the control signal is enabled and to generate a first sense amplifier driving voltage when the control signal is disabled; a switching control unit configured to generate a switching control signal when the control signal and a second sense amplifier enable signal are enabled; a second sense amplifier driving voltage generation unit configured to generate a second sense amplifier driving voltage when the second sense amplifier enable signal is enabled; and a switching unit configured to electrically couple a power line for the first sense amplifier and a power line for the second sense amplifier according to the switching control signal.
16. The semiconductor memory apparatus according to claim 15 , further comprising: a first sense amplifier configured electrically coupled to a first mat and configured to sense and amplify data stored in the first mat; and a second sense amplifier electrically coupled to a second mat and configured to sense and amplify data stored in the second mat.
17. The semiconductor memory apparatus according to claim 15 , wherein the mode control signal allows a refresh operation to be continuously performed.
18. The semiconductor memory apparatus according to claim 15 , further comprising: a latch section configured to output a level of the mode control signal when the refresh signal is enabled as a level of the control signal.
19. The semiconductor memory apparatus according to claim 15 , wherein the control signal generation unit is configured to retain an enabled state of the control signal until the voltage application enable signal is disabled when the refresh signal is enabled.
20. The semiconductor memory apparatus according to claim 15 , wherein the mode control signal allows a refresh operation to be performed one time when the refresh signal is disabled.
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December 9, 2014
December 15, 2015
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