Semiconductor memory device

1. A semiconductor memory device comprising: first and second memory cells that are stacked above a semiconductor substrate; third and fourth memory cells that are stacked above the first and second memory cells; first to fourth word lines that are electrically connected to gates of the first to fourth memory cells, respectively; and a row decoder configured to apply voltages to the first to fourth word lines, wherein the row decoder applies a first programming voltage to the first word line during a write operation performed on the first memory cell and applies the first programming voltage to the second word line during a write operation performed on the second memory cell, and the row decoder applies a second programming voltage that is higher than the first programming voltage to the third word line during a write operation performed on the third memory cell and applies the second programming voltage to the fourth word line during a write operation performed on the fourth memory cell.

2. The device according to claim 1 , wherein the write operation includes a programming operation during which a programming voltage is applied to a word line connected to a memory cell being programmed and a programming verifying operation, and the write operation is repeated if the programming verifying operation indicates that programming of the memory cell has failed.

3. The device according to claim 2 , wherein the programming voltage is stepped up each time the write operation is repeated, and the first and second programming voltages are initial programming voltages for the first and second memory cells, respectively.

4. The device according to claim 3 , wherein the write operation further includes a detecting operation to determine whether a threshold value of the first and second memory cells is greater than or equal to a first detection voltage, and to determine whether a threshold value of the third and fourth memory cells is greater than or equal to a second detection voltage that is higher than the first detection voltage.

5. The device according to claim 4 , wherein the detecting operation is performed after the write operation has been repeated a first number of times.

6. The device according to claim 5 , wherein each of the first to fourth memory cells is capable of holding more than two bits of data, and the write operation includes a lower bit write operation of the more than two bits of data, and a programming voltage used in the upper bit write operation is set in accordance with a result of the detecting operation.

7. The device according to claim 1 , further comprising: a conductive layer that is formed through the first to fourth word lines and has current paths of the first to fourth memory cells formed therein, wherein a diameter of the conductive layer increases in a direction from a lower end of the word lines to an upper end of the word lines.

8. The device according to claim 1 , further comprising: fifth and sixth memory cells that are stacked above a semiconductor substrate; seventh and eighth memory cells that are stacked above the fifth and sixth memory cells; and fifth to eighth word lines that are electrically connected to gates of the fifth to eighth memory cells, respectively, wherein the row decoder applies a third programming voltage to the fifth word line during a write operation performed on the fifth memory cell and applies the third programming voltage to the sixth word line during a write operation performed on the sixth memory cell, and the row decoder applies a fourth programming voltage that is higher than the third programming voltage to the seventh word line during a write operation performed on the seventh memory cell and applies the fourth programming voltage to the eighth word line during a write operation performed on the eighth memory cell.

9. The device according to claim 8 , wherein the fifth and sixth memory cells are stacked above the third and fourth memory cells and the third programming voltage is higher than the second programming voltage.

10. The device according to claim 8 , wherein the fifth and sixth memory cells are stacked above the third and fourth memory cells and the third programming voltage is lower than the second programming voltage.

11. The device according to claim 1 , wherein during the write operation performed on a selected memory cell, the row decoder applies pass voltages to unselected memory cells.

12. The device according to claim 11 , wherein a pass voltage applied to a fifth memory cell is greater than a pass voltage applied to a sixth memory cell that is closer to the substrate than the fifth memory cell.

13. The device according to claim 11 , wherein a pass voltage applied to a fifth memory cell is less than a pass voltage applied to a sixth memory cell that is closer to the substrate than the fifth memory cell and is a first number of memory cells away from the selected memory cell.

14. A semiconductor memory device comprising: a first memory cell that is provided above a semiconductor substrate; a second memory cell that is provided above the first memory cell; first and second word lines that are electrically connected to gates of the first and second memory cells, respectively, and a row decoder configured to apply voltages to the first and second word lines, wherein the write operation includes a programming operation during which a programming voltage is applied to a word line connected to a memory cell being programmed, a programming verifying operation to verify whether the programming of the memory cell has succeeded or failed, and a detecting operation to determine whether a threshold value of the memory cell is greater than or equal to a detection voltage, and the detection voltage for the first memory cell is a first detection voltage, and the detection voltage for the second memory cell is a second detection voltage that is higher than the first detection voltage.

15. The device according to claim 14 , wherein the programming operation is repeated if the programming verifying operation indicates that programming of the memory cell has failed, the detecting operation for the first memory cell is executed after the programming operation for the first memory cell is repeated a first number of times, and the detecting operation for the second memory cell is executed after the programming operation for the second memory cell is repeated a second number of times that is greater than the first number of times.

16. The device according to claim 15 , wherein each of the first and second memory cells is capable of holding more than two bits of data, and the write operation includes a lower bit write operation of the more than two bits of data, and a programming voltage used in the upper bit write operation is set in accordance with a result of the detecting operation.

17. The device according to claim 14 , further comprising: a conductive layer that is formed through the first and second word lines and has current paths of the first and second memory cells formed therein, wherein a diameter of the conductive layer increases in a direction from a lower end of the word lines to an upper end of the word lines.

18. A semiconductor memory device comprising: a plurality of memory cells that are stacked above a semiconductor substrate and divided into first and second groups, the first group of memory cells being located a first distance range away from the semiconductor substrate and the second group of memory cells being located a second distance range, not overlapping with the first distance range, away from the semiconductor substrate, the memory cells including first and second memory cells that are in the first group and third and fourth memory cells that are in the second group; a plurality of word lines that are connected to gates of the plurality of memory cells, respectively; and a row decoder configured to apply voltages to the plurality of word lines, wherein the row decoder applies a first programming voltage to the first word line during a write operation performed on the first memory cell and applies the first programming voltage to the second word line during a write operation performed on the second memory cell, and the row decoder applies a second programming voltage that is different from the first programming voltage to the third word line during a write operation performed on the third memory cell and applies the second programming voltage to the fourth word line during a write operation performed on the fourth memory cell.

19. The device according to claim 18 , wherein the first memory cell includes a first portion within a circular opening through a first word line and the second memory cell includes a second portion within a circular opening through a second word line, and a diameter of the first portion is less than a diameter of the second portion.

20. The device according to claim 19 , wherein the first and second memory cells are closer to the semiconductor substrate than the third and fourth memory cells.