Method and system for improving data integrity in non-volatile storage

1. A method for improving data integrity in a non-volatile memory system comprising: accessing non-volatile memory cells for retrieving hard data bits; decoding the hard data bits; and in response to a determination that decoding the hard data bits was not successful: generating soft information by capturing a reliability of the hard data bits, wherein generating the soft information includes loading a first read register with values of the hard data bits read using a first threshold voltage and loading a second read register, distinct from the first register, with values of the hard data bits read using a second threshold voltage, and comparing the contents of the first read register with the contents of the second read register; delivering the soft information and values from at least one of the first read register and second read register to an error correction module via a multiplexer; calculating syndrome bits by applying a lossy compression to the soft information; and generating host data by executing a low density parity check (LDPC) iterative decode on the hard data bits and the syndrome bits.

2. The method as claimed in claim 1 further comprising calculating probability bits from the syndrome bits.

3. The method as claimed in claim 1 wherein calculating the syndrome bits includes determining a number of unreliable bits and sending a syndrome 1 to a decompression module.

4. The method as claimed in claim 1 wherein executing the low density parity check (LDPC) iterative decode on the hard data bits and the syndrome bits includes calculating probability bits from the syndrome bits.

5. The method as claimed in claim 1 further comprising performing an iterative cycle decompression of the syndrome bits by transferring a second set of the syndrome bits.

6. A non-volatile memory system comprising: non-volatile memory cells, coupled to a destination register, for retrieving hard data bits, wherein the destination register includes a first read register, for loading hard data bits using a first threshold voltage, and a second read register, for loading values of the hard data bits read using a second threshold voltage; a reliability logic module, coupled to the destination register, for comparing the contents of the first read register with the contents of the second read register; a soft information module, coupled to the reliability logic module, for generating soft information by capturing a reliability of the hard data bits; a lossy compression module, coupled to the soft information module, for calculating syndrome bits by applying a lossy compression to the soft information; an error correction module, coupled to the lossy compression module, for generating host data by executing a low density parity check (LDPC) iterative decode on the hard data bits and the syndrome bits; and a multiplexer coupling at least one of the first read register and second read register to the error correction module; wherein the soft information module, lossy compression module and error correction module are configured to generate the soft information, calculate the syndrome bits and generate host data by executing the low density parity check iterative decode on the hard data bits and the syndrome bits in response to a determination that decoding the hard data bits was not successful.

7. The system as claimed in claim 6 further comprising a compute log likelihood ratio (LLR) module, coupled to the lossy compression module, for calculating probability bits from the syndrome bits.

8. The system as claimed in claim 6 wherein the lossy compression module, coupled to a multiplexer, is further for determining a number of unreliable bits and sending a syndrome to a decompression module.

9. The system as claimed in claim 6 wherein the error correction module, coupled to the lossy compression module, for generating host data includes a compute log likelihood ratio (LLR) module between the error correction module and the lossy compression module for calculating probability bits from the syndrome bits.

10. The system as claimed in claim 6 further comprising a decompression module configured to perform an iterative cycle decompression of the syndrome bits by transferring a second set of the syndrome bits having an incremented start location.

11. A non-volatile memory system comprising: a non-volatile memory device that includes: non-volatile memory cells having hard data bits; a destination register, coupled to the non-volatile memory cells, for retrieving the hard data bits, wherein the destination register includes a first read register, for loading hard data bits using a first threshold voltage, and a second read register, for loading values of the hard data bits read using a second threshold voltage; a reliability logic module, coupled to the destination register, for comparing the contents of the first read register with the contents of the second read register; a soft information module, coupled to the reliability logic module, for generating soft information by capturing a reliability of the hard data bits; and a lossy compression module, coupled to the soft information module, for calculating syndrome bits by applying a lossy compression to the soft information; and a controller module, coupled to the non-volatile memory device, the controller module including an error correction module for generating host data by executing a low density parity check (LDPC) iterative decode on the hard data bits and the syndrome bits; the non-volatile memory device further including a multiplexer coupling at least one of the first read register and second read register to the error correction module; wherein the soft information module, lossy compression module and error correction module are configured to generate the soft information, calculate the syndrome bits and generate host data by executing the low density parity check iterative decode on the hard data bits and the syndrome bits in response to a determination that decoding the hard data bits was not successful.

12. The system as claimed in claim 11 wherein the controller module further includes a compute log likelihood ratio (LLR) module for calculating probability bits from the syndrome bits.

13. The system as claimed in claim 11 wherein: the non-volatile memory device having the lossy compression module, coupled to the soft information module, is further for determining a number of unreliable bits and sending a syndrome; and the controller module further includes a decompression module for decompressing the syndrome.

14. The system as claimed in claim 11 wherein the controller module includes a compute log likelihood ratio (LLR) module for calculating probability bits, from the syndrome bits, for the error correction module.

15. The system as claimed in claim 11 wherein: the non-volatile memory device includes: a reliability logic module, coupled to the destination register, for calculating a soft information, and a multiplexer, coupled to the lossy compression module and the destination register, for transferring the hard data bits and the syndrome bits on a flash data bus; and the controller module includes a demultiplexer, coupled to the flash data bus, for separating the hard data bits and the syndrome bits from the flash data bus.