A method of forming a three-dimensional (3D) chip is provided in which a second chip is present embedded within a first chip. In one embodiment, the method includes forming a first chip including first electrical devices and forming a recess extending from a surface of the first chip. A second chip is formed having second electrical devices. The second chip is then encapsulated within the recess of the first chip. Interconnects are then formed through the first chip into electrical communication with at least one of the second devices on the second chip. A three-dimensional (3D) chip is also provided in which a second chip is embedded within a first chip.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of forming a device comprising: forming a recess in a first chip, the recess extending from a second chip surface of the first chip into the first chip, wherein the first chip includes first electrical devices; positioning a second chip within the recess of the first chip, wherein the second chip includes second electrical devices and contact pads electrically connected to the second electrical devices, the contact pads contacting a base of the recess; forming vias in the first chip after the second chip has been positioned within the recess, the vias comprising first vias extending from a first chip surface of the first chip that is opposite the second chip surface into a portion of the first chip to expose the contact pads of the second chip and second vias extending through an entire thickness of the first chip; and simultaneously forming first interconnects within the first vias and second interconnects within second vias, wherein the first interconnects are in direct contact with the contact pads of the second chip.
2. The method of claim 1 , wherein the first chip comprises a first body having a first protective layer on a first surface of the body and a second protective layer on a second surface of the first body, in which the first surface is opposite the second surface.
3. The method of claim 2 , wherein the first electrical devices include at least one of semiconductors devices, memory devices, resistors and capacitors, wherein the first electrical devices are present within or on the first body.
4. The method of claim 2 , wherein the forming of the recess in the first chip comprises forming an first etch mask on the second protective layer, etching the second protective layer, etching the first body to provide the recess; and forming a conformal dielectric layer on sidewalls and the base of the recess.
5. The method of claim 4 , wherein the etching of the second protective layer and the etching of the first body comprises an anisotropic etch process.
6. The method of claim 4 , wherein the second chip further comprises a second body and an interlevel dielectric layer present on a first surface of the second body, said contact pads extending through the interlevel dielectric layer into contact with the first surface of the second body.
7. The method of claim 6 , wherein the second chip includes second electrical devices selected from the group consisting of semiconductors devices, memory devices, resistors and capacitors, wherein the second electrical devices are present within or on the second body.
8. The method of claim 6 , wherein the positioning of the second chip within the recess of the first chip comprises contacting the contact pads of the second chip with the conformal dielectric layer on the base of the recess.
9. The method of claim 8 , wherein a second surface of the second body of the second chip that is opposite the first surface of the second chip is coplanar with the second chip surface of the first chip.
10. The method of claim 9 , wherein the forming of the interconnects comprises forming a second etch mask on the first protective layer of the first chip; etching the first protective layer, the first body, and the conformal dielectric layer selective to the contact pads of the second chip to provide the first vias and etching the first protective layer, the first body and the second protective layer to provide the second vias; forming a dielectric liner on sidewalls of the first and the second vias; and filling the first and the second vias with a conductive material to provide the first interconnects within the first vias and the second interconnects within the second vias.
11. The method of claim 10 , wherein the conductive material is composed of a metal or doped semiconductor material.
12. The method of claim 10 , further comprising forming an interconnect contact pad present on an upper surface of each of the interconnects.
13. The method of claim 12 , further comprising removing the second etch mask prior to forming the interconnect contact pad.
14. The method of claim 1 , wherein the second chip is encapsulated within the recess of the first chip.
15. The method of claim 1 , wherein a depth of the recess is smaller than a thickness of the second chip.
16. The method of claim 1 , wherein the second interconnects have a width greater than a width of the first interconnects.
17. The method of claim 1 , further comprising stacking at least one another device on the first chip having the second chip embedded therein, wherein the at least one another device is electrically connected to the first chip through said second interconnects.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 19, 2010
December 22, 2015
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