An electronic device includes a memory. The memory includes a first cell array including a plurality of flash memory cells, a first peripheral circuit suitable for controlling the first cell array, a second cell array including a plurality of variable resistance memory cells, and a second peripheral circuit suitable for controlling the second cell array. The first cell array, the first peripheral circuit, and the second peripheral circuit are formed at a first level over a surface of a semiconductor substrate, and the second cell array is disposed at a second level over the surface of a semiconductor substrate, the second level being higher than the first level. A portion of the second cell array overlaps in a plan view the second peripheral circuit and/or the first cell array.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An electronic device comprising a semiconductor memory unit, the semiconductor memory unit comprising: a first cell array including a plurality of flash memory cells disposed at a first level in a vertical direction to a substrate; a first peripheral circuit configured to control the first cell array and disposed at the first level; a second cell array including a plurality of variable resistance memory cells disposed at a second level which is higher than the first level in the vertical direction; and a second peripheral circuit configured to control the second cell array and disposed at the first level, wherein the second cell array overlaps the second peripheral circuit and the first cell array.
2. The electronic device according to claim 1 , wherein the first cell array is disposed between the first peripheral circuit and the second peripheral circuit.
3. The electronic device according to claim 1 , further comprising a multi-layer interconnect structure disposed between the second cell array and the second peripheral circuit and electrically coupling the second cell array to the second peripheral circuit.
4. The electronic device according to claim 1 , wherein the first peripheral circuit includes a first peripheral circuit transistor which is formed using the semiconductor substrate, and the second peripheral circuit includes a second peripheral circuit transistor which is formed using the semiconductor substrate, and the first cell array includes a cell transistor and a selection transistor each formed using the semiconductor substrate.
5. The electronic device according to claim 4 , wherein the cell transistor includes a first gate structure comprising a first tunnel insulation layer, a first floating gate disposed over the first tunnel insulation layer, a first charge blocking layer disposed over the first floating gate, and a first control gate disposed over the first charge blocking layer, and the first peripheral circuit transistor, the second peripheral circuit transistor and the selection transistor include a second gate structure comprising a second tunnel insulation layer, a second floating gate disposed over the second tunnel insulation layer, a second charge blocking layer disposed over the second floating gate, and a second control gate disposed over the second charge blocking layer, wherein at least a portion of the second charge blocking layer is absent so that the second floating gate and the second control gate are electrically coupled.
6. The electronic device according to claim 1 , wherein the second cell array includes: a plurality of first lines extending in a first horizontal direction; a plurality of second lines disposed over the first lines extending in a second horizontal direction and intersecting the first lines; and a plurality of variable resistance elements disposed between the first lines and the second lines at intersections of the first lines and the second lines.
7. The electronic device according to claim 6 , wherein the first and second lines are electrically coupled to the second peripheral circuit through a multi-layer interconnect structure disposed between the second cell array and the second peripheral circuit in a region where the second cell array and the second peripheral circuit overlap with each other, and at least one of the first lines and second lines extend to overlap with the first cell array.
8. The electronic device according to claim 6 , wherein the plurality of variable resistance elements is a first plurality of variable resistance elements, and the second cell array further includes: a plurality of third lines disposed over the second lines, extending in the first horizontal direction, and overlapping the plurality of first lines; and a second plurality of variable resistance elements disposed between the second lines and third lines at intersections of the second lines and the third lines.
9. The electronic device according to claim 1 , wherein the first cell array includes a cell transistor and a selection transistor, and the second cell array includes a plurality of first lines which extend in a first horizontal direction, a plurality of second lines disposed over the first lines, extending in a second horizontal direction, and intersecting the first lines, and variable resistance elements which are disposed between the first lines and the second lines at intersections of the first lines and the second lines, and a first matrix region wherein the cell transistor and the selection transistor are arranged overlaps with a portion of a second matrix region wherein the variable resistance elements are arranged.
10. The electronic device according to claim 9 , wherein the first cell array is electrically coupled to a first other circuit through a conductor disposed in a region external to the first matrix region, and the second cell array is electrically coupled to a second other circuit through a conductor disposed in a region external to the second matrix region.
11. The electronic device according to claim 1 , wherein the first cell array and the first peripheral circuit function as a memory for storing user data, and the second cell array and the second peripheral circuit function as a buffer memory for assisting a data input/output of the memory.
12. The electronic device according to claim 1 , wherein the first cell array and the first peripheral circuit function as a first memory for storing user data, and the second cell array and the second peripheral circuit function as a second memory for storing user data.
13. The electronic device according to claim 1 , wherein the second cell array further overlaps the first peripheral circuit.
14. An electronic device comprising a semiconductor memory unit, the semiconductor memory unit comprising: a semiconductor substrate including a first region and a second region; a peripheral circuit transistor disposed in the first region; a cell transistor and a selection transistor of a flash memory each disposed in the second region; a plurality of first lines disposed over the peripheral circuit transistor and extending in a first horizontal direction parallel to a surface of the semiconductor substrate; a plurality of second lines extending in a second horizontal direction and intersecting with the first lines over the first lines; and a plurality of variable resistance elements disposed between the first lines and the second lines at cross points of the first lines and the second lines, wherein the first and second lines are electrically coupled to the peripheral circuit transistor through a conductor disposed in the first region, and at least one of the first lines and second lines extends to the second region.
15. The electronic device according to claim 14 , wherein the peripheral circuit transistor is a second peripheral circuit transistor, and wherein the semiconductor substrate further includes a third region and a first peripheral circuit transistor disposed in the third region.
16. The electronic device according to claim 15 , wherein the second region is disposed adjacent to the first region between the first region and the third region.
17. The electronic device according to claim 14 , wherein the cell transistor includes a first gate structure wherein a tunnel insulation layer, a floating gate, a charge blocking layer and a control gate are stacked, and the peripheral circuit transistor and the selection transistor each include a second gate structure in which the tunnel insulation layer, the floating gate, the charge blocking layer and the control gate are stacked, wherein at least a portion of the charge blocking layer of the second gate structure is absent from the second gate structure so that the floating gate and the control gate of the second gate structure are electrically coupled.
18. The electronic device according to claim 14 , wherein a first matrix region where the cell transistor and the selection transistor are disposed overlaps with a portion of a second matrix region where the variable resistance elements are disposed.
19. The electronic device according to claim 18 , wherein a gate of the cell transistor and a gate of the selection transistor are electrically coupled to a first other circuit through conductors disposed in a region external to the first matrix region, and the first and second lines are electrically coupled to a second other circuit through conductors disposed in a region external to the second matrix region.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 7, 2014
December 22, 2015
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