Subject matter disclosed herein may relate to word line electrodes and/or digit line electrodes in a cross-point array memory device. One or more word line electrodes may be configured to form a socket area to provide connection points to drivers and/or other circuitry that may be located within a footprint of an array of memory cells.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An integrated circuit comprising a socket region in which vertical connections are made to a metal level, the integrated circuit comprising: a plurality of conductive lines extending parallel to one another along a first direction outside of the socket region; a first subset of the conductive lines extending in the first direction and terminating at the socket region, wherein the first subset of the conductive lines includes at least two conductive lines that co-terminate at substantially the same position along the first direction, and the first subset of the conductive lines further includes at least one conductive line that does not co-terminate with the at least two conductive lines and extends farther along the first direction into the socket region; a second subset of the conductive lines that extend through the socket region, wherein each conductive line of the second subset of the conductive lines includes a jog segment within the socket region, each jog segment deviating from parallel to the first direction; and a plurality of conductive vertical connectors positioned within the socket region, at least one of the conductive vertical connectors contacting one of the jog segments of the second subset of the conductive lines.
2. The integrated circuit of claim 1 , wherein the at least one conductive line that does not co-terminate deviates substantially from parallel to the first direction before terminating.
3. The integrated circuit of claim 1 , wherein a smallest lateral dimension of the conductive vertical connectors is at least twice a minimum feature size F, wherein F is a minimum feature size of a memory array.
4. The integrated circuit of claim 1 , wherein a shortest distance from an edge of one of the at least two conductive lines that co-terminate to an opposite edge of an immediately adjacent conductive line that does not co-terminate in a direction perpendicular to the first direction is substantially equal to a minimum feature size F, wherein F is a minimum feature size of a memory array.
5. The integrated circuit of claim 1 , wherein a shortest distance from an edge of one jog segment to a corresponding edge of an immediately adjacent jog segment in the first direction is at least four times the minimum feature size F.
6. The integrated circuit of claim 1 , wherein the first subset of the conductive lines or the second subset of the conductive lines form a bundle of at least four conductive lines.
7. The integrated circuit of claim 1 , wherein a first group of the second subset of the conductive lines has jog segments deviating from the first direction towards a first side and a second group of the second subset of the conductive lines has jog segments deviating from the first direction towards a second side, the second side being opposite to the first side.
8. The integrated circuit of claim 1 , wherein the conductive lines are memory word lines, the integrated circuit further comprising one or more memory digit lines positioned along a direction substantially orthogonal to the first direction.
9. The integrated circuit of claim 8 , further comprising one or more word line drivers and/or one or more digit line drivers positioned in a semiconductor material and arranged in an at least partially repeating pattern of substantially alternating word line drivers and/or digit line drivers.
10. The integrated circuit of claim 9 , wherein the word line drivers are electrically coupled to the memory word lines at a substantially central location of the memory word lines and the digit line drivers are electrically coupled to the memory digit lines at a substantially central location of the digit lines.
11. The integrated circuit of claim 9 , wherein the at least partially repeating pattern comprises a mirroring pattern of word line drivers and bit line drivers.
12. The integrated circuit of claim 9 , wherein the integrated circuit comprises an array of memory cells, the array of memory cells comprising an array of phase change memory storage elements.
13. The integrated circuit of claim 9 , wherein the integrated circuit comprises an array of memory cells, the array of memory cells comprising an array of phase change memory storage elements coupled to chalcogenide switches configured as a cross-point array.
14. The integrated circuit of claim 9 , wherein the integrated circuit comprises an array of memory cells, the array of memory cells comprising an array of resistive memory storage elements.
15. The integrated circuit of claim 12 , further comprising one or more metallization levels positioned between the semiconductor material and the array of memory cells, wherein the one or more metallization levels comprise an upper metallization level having a pitch greater than a memory cell pitch of the array of memory cells.
16. The integrated circuit of claim 12 , wherein the array of memory cells comprises more than one deck of memory.
17. The integrated circuit of claim 1 , further comprising: a plurality of upper conductive lines in a level vertically above the plurality of conductive lines and the metal level, the upper conductive lines extending parallel to the first direction, wherein each of the upper conductive lines includes a second jog segment deviating from parallel to the first direction, wherein the conductive vertical connectors include a first subset of the conductive vertical connectors connecting the one of the jog segments of the second subset of the conductive lines to the metal level, and further including a second subset of the conductive vertical connectors connecting one of the second jog segments to the metal level.
18. The integrated circuit of claim 17 , wherein the first subset of conductive lines and the second subset of conductive lines comprise first memory word lines of a lower deck memory array, the integrated circuit further comprising one or more memory digit lines of the lower deck memory array positioned along a direction substantially orthogonal to the first direction.
19. The integrated circuit of claim 18 , wherein the upper conductive lines comprise second memory word lines of an upper deck memory array.
20. The integrated circuit of claim 18 , wherein at least one memory digit line of the lower deck memory array is also a digit line of the upper deck memory array.
21. The integrated circuit of claim 19 , wherein the first memory word lines of the lower deck memory array at least partially overlaps horizontal positions of the second memory word lines of the upper deck memory array within the socket region.
22. The integrated circuit of claim 17 , wherein the horizontal positions of the jog segments and the second jog segments do not overlap such that the first subset of conductive vertical connectors and the second subset of conductive vertical connectors make independent connections to the metal level.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 26, 2013
December 29, 2015
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