A method of manufacturing a semiconductor package having a magnetic shield function is provided. The method includes forming cracks in a lattice structure on an active surface in which electrode terminals are formed; grinding a back surface of a wafer facing the active surface, bonding a tape on the active surface of the wafer, expanding the tape such that the wafer on the tape is divided as semiconductor chips, forming a shield layer on surfaces of the semiconductor chips and the tape, cutting the shield layer between the semiconductor chips and individualizing as each of the semiconductor chips which has a first shield pattern formed on back surface and sides, bonding the semiconductor chips on a substrate, and forming a second shield pattern on each of the active surfaces of the semiconductor chips, wherein the semiconductor chips and the substrate are physically and electrically connected by a bonding wire.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of manufacturing a semiconductor package, comprising: forming cracks in a lattice structure on an active surface of a wafer in which electrode terminals are formed; grinding a back surface of the wafer facing the active surface; bonding a tape on the active surface of the wafer; expanding the tape such that the wafer on the tape is divided into a plurality of sections, each section corresponding to a semiconductor chip; forming a shield layer on surfaces of the semiconductor chips and the tape; cutting the shield layer between the semiconductor chips, and sectioning off each of the semiconductor chips, each semiconductor chip having an active surface and a first shield pattern on a back surface and sides thereof; bonding the semiconductor chips to a substrate; and forming a second shield pattern on each active surface of the semiconductor chips, wherein the semiconductor chips and the substrate are connected by a bonding wire.
2. The method of manufacturing the semiconductor package according to claim 1 , wherein the forming of the cracks in the lattice structure of the wafer comprises irradiating the active surface of the wafer with a laser beam.
3. The method of manufacturing the semiconductor package according to claim 1 , wherein the bonding of the semiconductor chips to the substrate comprises bonding an adhesive film on an upper surface of the shield layer, forming a first bonding layer on a lower surface of the first shield pattern by contemporaneously cutting the shield layer and the adhesive film, and bonding the first bonding layer to the substrate.
4. The method of manufacturing the semiconductor package according to claim 1 , further comprising forming a buffer layer between the semiconductor chips and the shield layer.
5. The method of manufacturing the semiconductor package according to claim 1 , further comprising: forming a molding enveloping the semiconductor chips and the bonding wire; and cutting the molding and the substrate, and sectioning off one or more single semiconductor package each including a semiconductor chip.
6. The method of manufacturing the semiconductor package according to claim 1 , further comprising stacking another substantially identical semiconductor chip on the semiconductor chip and between the semiconductor chip and the second shield pattern.
7. The method of manufacturing the semiconductor package according to claim 6 , further comprising forming an inter chip bonding layer between the stacked semiconductor chips to cover one end of the bonding wire and to bond the stacked semiconductor chips.
8. The method of manufacturing the semiconductor package according to claim 7 , wherein the inter chip bonding layer comprises at least one of an epoxy-based resin and a silicon-based resin.
9. The method of manufacturing the semiconductor package according to claim 1 , wherein the forming of the second shield pattern comprises bonding the previously manufactured second shield pattern in the form of a thin film on the surfaces of the semiconductor chips.
10. The method of manufacturing the semiconductor package according to claim 1 , wherein at least one of the first shield pattern and the second shield pattern comprises permalloy.
11. A method of manufacturing a semiconductor package, comprising: preparing a semiconductor wafer having an active surface in which electrode terminals are formed, and a back surface opposite the active surface; forming a first shield layer on portions of the active surface that do not include the electrode terminals; grinding the back surface of the wafer; cutting the wafer including the first shield layer, and sectioning off a plurality of semiconductor chips each having a first shield pattern formed on the active surface; bonding the semiconductor chips to a carrier so that back sides and sides of the semiconductor chips are exposed; forming a second shield layer on the back surface and sides of the semiconductor chips and on an upper surface of the carrier; forming a molding layer on an upper surface of the second shield layer; and removing the carrier.
12. The method of manufacturing the semiconductor package according to claim 11 , wherein the forming of the first shield layer comprises: forming mask patterns each having a wider area than a surface area of each corresponding electrode terminal and covering the electrode terminals; conformally forming a first shield layer on a surface of a protective layer which is not covered by the mask patterns and on surfaces of the mask patterns; and keeping the first shield layer only on portions of the surface of the protective layer that do not include the electrode terminals by removing the mask patterns.
13. The method of manufacturing the semiconductor package according to claim 11 , further comprising forming an interlayer insulating layer covering the first shield layer and exposing the electrode terminals.
14. The method of manufacturing the semiconductor package according to claim 11 , further comprising forming a rewiring unit including vias connected to the electrode terminals, signal wirings connected to the vias, and lands connected to the signal wirings and formed at an outside edge of the semiconductor wafer.
15. The method of manufacturing the semiconductor package according to claim 14 , further comprising cutting the molding layer, the second shield layer, and the rewiring unit between the semiconductor chips, sectioning off at least one single semiconductor package, and providing a second shield pattern covering the back surfaces and sides of the semiconductor chips and a molding covering the second shield pattern.
16. A method of manufacturing a magnetically shielded semiconductor package, comprising: forming one or more fissures in a lattice structure of a wafer on an active surface thereof; thinning the wafer; forming a layer at the active surface of the wafer; sectioning the wafer on the layer into a plurality of sections, each section corresponding to a semiconductor chip; forming a first shield layer on surfaces of the semiconductor chips and the layer; sectioning off each of the semiconductor chips, each semiconductor chip having an active surface and a first shield pattern on a back surface and sides thereof; bonding one or more of the semiconductor chips to a substrate; and forming a second shield pattern on the active surface of each of the one or more semiconductor chips.
17. The method of claim 16 , wherein thinning the wafer comprises having a wafer thickness such that the one or more fissures extend from the active surface to the back surface of the wafer.
18. The method of claim 16 , wherein: forming the layer comprises bonding a tape to the active surface of the wafer; and sectioning the wafer comprises expanding the bonding tape in at least one direction parallel to the active surface.
19. The method of claim 16 , wherein the second shield pattern is formed on the active surface of the one or more semiconductor chips via a bonding layer.
20. The method of claim 16 , further comprising: covering one or more of the semiconductor chips by a molding; and sectioning off the molding to form one or more molding layers corresponding to the one or more semiconductor chips.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 18, 2014
December 29, 2015
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