Patentable/Patents/US-9229059
US-9229059

Memory test system and method

PublishedJanuary 5, 2016
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

An exemplary embodiment of the present disclosure illustrates a memory test system comprising a memory device, a probe card, and a tester. The memory device comprises a memory die with a plurality of memory banks, a plurality of input circuits, and a plurality of output circuits, wherein each of the input circuits has a first input pin and a second pin, the first input pins of the input circuits are used to read a plurality of patches of data stored in memory cells of the memory banks, and the second input pins are used to receive a compressed result. The output circuits receive compressed signals output from the input circuits, and the probe card mixes the compressed output signals output from the output circuits to output a mixed compressed output signal to the tester.

Patent Claims
5 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A memory test system, comprising: a memory device, comprising a memory die with a plurality of memory banks, a plurality of input circuits, and a plurality of output circuits, wherein each of the input circuits has a first input pin and a second pin, the first input pins of the input circuits are used to read a plurality of patches of data stored in memory cells of the memory banks, and the second input pins are used to receive a compressed result; a probe card, electrically connected to the output circuits; and a tester, electrically connected to the probe card; wherein the output circuits receive compressed signals output from the input circuits, and the probe card mixes compressed output signals output from the output circuits to output a mixed compressed output signal to the tester.

2

2. The memory test system according to claim 1 , wherein the input circuits are buffers.

3

3. The memory test system according to claim 1 , wherein the first input pins are input/output pins.

4

4. The memory test system according to claim 1 , wherein the output circuits are off-chip drivers.

5

5. The memory test system according to claim 1 , wherein the memory device is a dynamic random access memory.

Classification Codes (CPC)

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Patent Metadata

Filing Date

December 6, 2013

Publication Date

January 5, 2016

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Cite as: Patentable. “Memory test system and method” (US-9229059). https://patentable.app/patents/US-9229059

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