An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a low-k (LK) dielectric layer over a substrate; a first conductive feature and a second conductive feature in the LK dielectric layer; a first spacer along a first sidewall of the first conductive feature; a second spacer along a second sidewall of the second conductive feature, wherein the second sidewall of the second conductive feature faces the first sidewall of the first conductive feature; an air gap between the first spacer and the second spacer; and a third conductive feature over the first conductive feature, wherein the third conductive feature is connected to the first conductive feature.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An interconnect structure, comprising: a first low-k (LK) dielectric layer; a second LK dielectric layer over the first LK dielectric layer; a first conductive feature and a second conductive feature in the second LK dielectric layer; a first spacer along a first sidewall of the first conductive feature; a second spacer along a second sidewall of the second conductive feature, wherein the second sidewall of the second conductive feature faces the first sidewall of the first conductive feature; an air gap between the first spacer and the second spacer, wherein the second LK dielectric layer extends at least in part between the first spacer and the air gap, between the second spacer and the air gap, or both; and a third conductive feature over the first conductive feature, wherein the third conductive feature is connected to the first conductive feature.
2. The interconnect structure of claim 1 , wherein the first LK dielectric layer and the second LK dielectric layer comprise a same material.
3. The interconnect structure of claim 1 , wherein an aspect ratio is a height of the first spacer or the second spacer divided by a spacing between the first spacer and the second spacer, the aspect ratio being greater than or equal to about 2.
4. The interconnect structure of claim 1 , wherein the first spacer or the second spacer has a thickness in a range from about 50 angstroms (Å) to about 80 angstroms (Å).
5. The interconnect structure of claim 1 , wherein the third conductive feature is spaced away from the air gap.
6. The interconnect structure of claim 1 , wherein the third conductive feature is further connected to the first spacer.
7. The interconnect structure of claim 1 , wherein: the first conductive feature is a first metal line; the second conductive feature is a second metal line; and the third conductive feature comprises a third metal line and a via contiguous with the third metal line.
8. The interconnect structure of claim 1 , further comprising a second etch stop layer (ESL) between a first portion and a second portion of the second LK dielectric layer.
9. The interconnect structure of claim 1 , further comprising a first etch stop layer (ESL) between the first LK dielectric layer and the second LK dielectric layer.
10. The interconnect structure of claim 1 , wherein the first spacer or the second spacer comprises a metal compound.
11. The interconnect structure of claim 10 , wherein the metal compound comprises a metal oxide, a metal nitride, a metal carbide, a metal boride, or a combination of two or more thereof.
12. An interconnect structure, comprising: a first low-k (LK) dielectric layer; a second LK dielectric layer over the first LK dielectric layer; a first conductive feature and a second conductive feature in the second LK dielectric layer; a first spacer along a first sidewall of the first conductive feature; a second spacer along a second sidewall of the second conductive feature, wherein the second sidewall of the second conductive feature faces the first sidewall of the first conductive feature, wherein the first spacer or the second spacer has a thickness greater than or equal to about 50 angstroms (Å); an air gap in the second LK dielectric layer between the first spacer and the second spacer; a third LK dielectric layer over the second LK dielectric layer; and a third conductive feature over the first conductive feature, wherein the third conductive feature is connected to the first conductive feature and spaced away from the air gap.
13. The interconnect structure of claim 12 , wherein an aspect ratio is a height of the first spacer or the second spacer divided by a spacing between the first spacer and the second spacer, the aspect ratio being greater than or equal to about 2.
14. The interconnect structure of claim 12 , wherein the first spacer or the second spacer comprises a metal compound selected from a metal oxide, a metal nitride, a metal carbide, a metal boride, or a combination of two or more thereof.
15. The interconnect structure of claim 12 , wherein the first spacer or the second spacer has a thickness in a range from about 50 angstroms (Å) to about 80 angstroms (Å).
16. The interconnect structure of claim 12 , further comprising at least one of: a first etch stop layer (ESL) between the first LK dielectric layer and the second LK dielectric layer; or an second ESL between the second LK dielectric layer and the third LK dielectric layer.
17. A method of forming an interconnect structure, comprising: forming a first conductive feature and a second conductive feature over a first low-k (LK) dielectric layer; forming a first spacer along a first sidewall of the first conductive feature and a second spacer along a second sidewall of the second conductive feature, wherein the second sidewall of the second conductive feature faces the first sidewall of the first conductive feature; depositing a second LK dielectric layer over the first LK dielectric layer to form an air gap between the first spacer and the second spacer, wherein the second LK dielectric layer extends at least in part between the first spacer and the air gap, between the second spacer and the air gap, or both; and forming a third conductive feature over the first conductive feature, wherein the third conductive feature is connected to the first conductive feature.
18. The method of claim 17 , wherein the step of forming a first spacer along a first sidewall of the first conductive feature and a second spacer along a second sidewall of the second conductive feature comprises: forming a spacer layer conformally over the first conductive feature, the second conductive feature, and the first LK dielectric layer; and removing horizontal portions of the spacer layer to form the first spacer and the second spacer.
19. The method of claim 18 , further comprising: forming a first etch stop layer (ESL) between the second LK dielectric layer and the first LK dielectric layer.
20. The method of claim 18 , further comprising: forming a second etch stop layer (ESL) between a first portion and a second portion of the second LK dielectric layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 30, 2013
January 5, 2016
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